CMOS NAND Gate Circuit

The CMOS NAND Gate Circuit

As stated earlier, CMOS NAND is a combination of an NMOS NAND gate with a PMOS NOR gate as its load or vice versa. The circuit of the CMOS NAND is shown in Fig. 3.27. As shown in Fig. 3.27, both the input terminals A of transistors T1N and T1P are shorted together to form the single input terminal A. Similarly, both the input terminals B of T2N and T2P are shorted to form the single input B. Let A = 0, B = 0. In this case, both the PMOS transistors conduct and the NMOS transistors remain OFF. So, output Z = +VDD ≡ logic 1. Also, when one of the inputs (A or B) is 0 and the other (B or A) is 1, the same situation prevails. However, if both A = B = 1, then the NMOS FETs conduct and PMOS FETs remain OFF. Then the output falls to logic 0. This is NAND operation.