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Monday, 22 July 2019

Block Diagram of Microcontroller 8051

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Block Diagram of Microcontroller 8051



CPU – The CPU (Central Processing Unit) comprising of ALU (Arithmetic and Logic Units) and Control units

ALU - Arithmetic and Logic Unit performing the arithmetic and logical operations. These operations are multiplication, addition, subtraction, logical AND,OR etc. To do these operations one operand must be in Accumulator, and another may in B register or in general purpose register. The ALU operation results are mostly placed in A register. Some results are placed in B register too.

OSC - Oscillator provides clock for controller operation .Crystal oscillator is used for providing perfect clock and stability. So this microcontroller uses crystal oscillator. For this purpose, the crystals linked to the pins are used.

INTERRUPT CONTROLLER

Microcontroller operation needs some interrupts. Here mainly five interrupts are used. The controller controls the operation interrupts. ie some interrupts may be allowed, some others are disabled and priority assigned and changed. The five interrupts are:

BUS CONTROL

For both Address and data, lower byte address buses are used. The BUS control controls the BUS usage. There are 3 control signals: PSEN , EA, and ALE. The signals like Program Store Enable (PSEN), Address Latch Enable (ALE) and External Access (EA),  are used for external memory interfacing.



ON CHIP RAM

The 8051 has 4 kilobyte of inbuilt ROM. It is otherwise called program memory. Usually program-code is stored in ROM. To store program into ROM, programmer is needed. If more area is required in ROM, an external ROM may be connected. Maximum of 64kb ROM memory can be used.

ON CHIP ROM

The 8051 has an inbuilt of 128 byte RAM, some version have 256 byte and are used as data memory. If the system needs more memory, external RAM may be connected up to 64kb.In 128 byte RAM chip, 00h to 71Fh are the address range .In this range ,00H to 1FH are the general purpose registers . 20H to 2F are the bit Addressable area and rest of this is byte addressable .This is used as general purpose scratch pad. In 256 byte RAM chip, another 128 bytes are used for Special Function Registers.

I/O PORTS

There are four IO ports in 8051.These are named as P0, P1, P2, P3.All are bidirectional. Each port have its address, output driver, latch and input buffer. Each port is output by default.

SERIAL PORT

TXD and RXD are utilised for serial port. Each pin has separate buffer registers named as SBUF.

TIMER/COUNTER

There are two types of counter/timer in 8051.These counter/timers are name as Timer/Counter 0 and Timer/Counter 1. Each one can be used as either Timer or Counter. 16 bit timer register are used for counting in timer operation or counter operation. Clock pulses are counted in Timer operation and external events are counted in counter operation.


Sunday, 21 July 2019

Properties of Conducting Materials

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PROPERTIES OF CONDUCTING MATERIALS:

1. Conductivity (σ) :

The conductivity (σ) is the reciprocal of electrical resistivity of the material. The units of conductivity are mhos/cm. It is the property of a material due to which the electric current flows easily through the material. In other words it provides an easy path to the flow of electric current through the material.

2. Tensile Strength :

Strength of a material is defined as the ability to resist load without failure. Tensile strength is therefore tie ability of the material resist a stretching (tensile) load without fracture. Therefore the tensile strength gives an indication of the conductor limit within which it has to be used and beyond which excessive deformation or fracture takes place. It is expressed in load per unit cross sectional area. (tonnes / cm2).

3. Ductility :

It is the ability of the material to be deformed plastically without rupture under tensile load. A ductile material can be drawn out into a fine wire without fracture and can also be bent, twisted or changed in shape without fracture. Gold, silver, copper, aluminium, nickel, tin, lead etc., are ductile materials.

4. Corrosion Resistance :

Corrosion is a gradual process in a material due to electro-chemical attack. Due to the chemicals present in the atmosphere and if the material is exposed, the metal is generally converted into an oxide, salt or some other compound, thus the metal- does not serve the purpose it is intended to. It may also occur in elevated temperature in media which are inert when near or below the room temperature.



5. Effect of Alloying on Resistivity :

Any impurity whether metallic or non-metallic increases resistivity. The effect of metal impurities on resistivity of a given metal is dependent on the nature of alloy formed. When the metal differs widely in atomic volumes and melting points the alloy comprises of crystals of both metals. Such alloys are called mechanical mixtures. The resistivity and temperature co-efficient of resistivity in these alloys vary linearly with percentage content of impurity.

When the atomic volumes of both do not differ by more than 15% the alloy comprises of single crystal in structure in which the crystal lattice accommodates the atoms of both metals. This is called solid solution alloy. In this type of alloy, the resistivity increases and temperature co-efficient decreases upon certain percentage of impurity content. After this, if the impurity is increased the resistivity decreases and temperature co-efficient increases.

When the metals combine chemically, it is called chemically combined alloy. The variation of resistivity and temperature co-efficient of resistivity with percentage of impurity content is very complicated. The alloying will increase the mechanical strength to a considerable extent and the material will become hard.

6. Effect of Alloying on Mechanical Properties :

Addition of even a small percentage of certain alloys improves mechanical and physical properties. Some of the effects are summarized below:

(a) Copper : It increase the strength and hardness and lowers the ductility. It also increases the corrosion resistance.

(b) Aluminium: It acts as de-oxider and restricts grain growth and aids nitriding.

(c) Lead : It increases machinability.

(d) Nickel : It increases tensile strength without sacrificing ductility. Increases toughness lowers the co-efficient of thermal expansion. Increases hardness slightly and decreases rusting.

(e) Tungsten : Carbide forming tendency high inhibits grain growth and considerably increases cohesive force.

(f) Silicon : Improves magnetic permeability and electrical resistivity. Increases the resistance to oxidization. Raises the ultimate strength. Acts as a ferrite strengthener.

(g) Chromium : Increases strength and hardness without affecting ductility. Increases wear and corrosion resistance. Increases the critical temperature and improves toughness.

(h) Manganese : Lowers melting point of iron decreases critical temperature increases the hardenability of steel.

(i) Cobalt : Imparts excellent magnetic properties, increases hardness in high speed steel.

7. Solderability :

Solder is a fusible alloy used to join the surfaces of metals. The property is useful at places where the two pieces of metals are to be joined as in the case of wires.

8. Brittleness:

It is opposite to the property of toughness and is the tendency of a metal to break on receiving a hammer blow. The brittle material has a poor resistance to shock loads.


Saturday, 20 July 2019

Schering Bridge with Formula

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The capacitance can be measured using Schering bridge. It is a widely used bridge for the measurement of capacitance. This bridge though is used for measuring capacitance is very useful in measuring insulation properties i.e. for phase angles very near to 90°. The schematic representation to this bridge is shown in Figure. One of the ratio arms contains a parallel combination of capacitor and resistor C1 and R1. The other ratio arm consists of a variable resistor R2. The standard arm consists of a capacitance of fixed value C3. Mica capacitor or well designed air dielectric type capacitor are used. The reason for the choice is the phase angle of the two having a value nearing 90°.

To obtain balance the sum of the phase angles of arms 1 and 4 must be equal to the sum of the phase angles of arms 2 and 3. As we have a standard capacitor in arm 3 the sum of the phase angles of arm 2 and 3 will be 0° + 90°. In order to obtain the 90° phase angle needed for balance the sum of angles of arm 1 and arm 4 must be equal to 90°. As the unknown capacitor will have a phase angle smaller than 90° arm must be provided with a small capacitive angle. This is done by providing a capacitor C1 parallel with R1. Schering bridge formula is derived as follows
SCHERING BRIDGE

The balance equation can be derived as follows :

Substituting the impedance and admittance values in the general formula, Zx = Z2 Z3 Y1
or 

Rx –j/ωCx = R2(-j/ωC3)(1/R1 + jωC1)

Expanding Rx –j/ωCx = R2C1/C3 – jR2/ωC3R1 --------------------------- 1

Equating real terms:

Rx = R2 C1/C3 ----------------------------------- 2

Equating imaginary terms,

Cx = C3 R1/R2 ----------------------------- 3



The two variables chosen for the balance adjustment are C1 and resistor R2. The dial of the capacitor C2 can be calibrated in terms of dissipation factor D, by keeping the value of R1 fixed. This can be explained as follows :

The power factor of a series RC combination is defined as the cosine of the phase angle of the circuit. Therefore the power factor of the unknown equals PF = Rx/Zx. For phase angles very close to 90°, the reactance is very nearly equal to the impedance and with a close approximation the power factor can be taken

PF = Rx/ Xx = ωCxRx ---------------------------- 4

The dissipation factor of a series RC circuit is explained as cotangent of the phase angle and hence by explanation the dissipation factor.

D = Rx/ Xx = ωCxRx     ---------------------------------------- 5

The quality factor of a coil is defined by Q = XL/RL, the dissipation factor, D is the reciprocal of the quality factor, Q and therefore D = I/Q. If we substitute the value of Cx in equation (3), and of Rx in equation (2), into the expression for the dissipation factor we obtain.

D = ωR1C1 -------------------------------- 6

Therefore keeping the value of R1 in the bridge fixed, the dial of capacitor C1 can be calibrated directly in dissipation factor D. One point to be noted here is that the term co appears in the equation for the dissipation factor D. Hence the calibration of the capacitor C1 is valid for one frequency at which it is calibrated. When a different frequency is used a correction can be made by multiplying the C1 dial reading by the ratio of the two frequencies. This is the advantage of using Schering bridge.


Thursday, 11 July 2019

Interrupts in 8085 Notes

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The signals requesting the microprocessor to perform a particular task or work, send by an external device is known as interrupts. For transferring data between the peripheral and the microprocessor, interrupts are mainly used.Here we can discuss about interrupts in 8085 notes. The interrupts are checked by the microprocessors always at the 2nd T-state of last machine cycle. If an interrupt occurs, it accepts the interrupt and sends the INTR signal to the peripheral. The microprocessor executes an interrupt service routine (ISR) stored in memory. It returns to the main program by RET instruction, after the ISR is executed. The interrupt process is shown in figure.
Interrupt process

Types of Interrupts:

There are six types of Interrupts in 8085. They are,

1. Hardware interrupts
2. Software interrupts
3. Maskable interrupts
4. Non-Maskable interrupts
5. Vectored interrupts
6. Non-vectored interrupts

Hardware interrupts: These interrupts are given by the peripheral devices to the interrupt pin (hardware) of the microprocessor. Hardware interrupts are also called external interrupts.

Software interrupts: These interrupts are internally generated within the microprocessor using software instructions. Software interrupts are also called internal interrupts.

Maskable interrupts: These external interrupts can be delayed or rejected by the microprocessor.

Non-maskable interrupts: These external interrupts cannot be delayed or rejected by the microprocessor. Non-maskable interrupts are used for handling emergency situations.

Vectored interrupts : When the address of the Interrupt Service Routine (ISR) is fixed within the microprocessor itself, then the interrupt is called Vectored interrupt.

Non-vectored interrupts : When the address of the Interrupt Service Routine (ISR) is supplied by the peripheral device, then the interrupt is called Non-vectored interrupt.

8085 interrupts


In 8085 microprocessor, there are 5 interrupts as shown in figure.

1. TRAP
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. INTR
8085 Interrupts

Notes: In additional to these hardware interrupts, 8085 microprocessor has eight software interrupts. The RESTART instructions RST 0 to RST 7 are software interrupt instructions.

Interrupt priority:


The microprocessor can respond to only one interrupt at one time. When multiple (more than one) interrupts occur simultaneously, the microprocessor will service the interrupts in their fixed priority order. Interrupt having the highest priority level will be serviced first. In 8085, TRAP interrupt has the highest priority and INTR has the lowest priority.




TRAP

• This interrupt can be considered as a non-maskable interrupt. Any mask or interrupt enable cannot affect this.
• It is a vectored interrupt. The interrupt vector address is 0024H.
• TRAP has the highest priority level.
• We can say that TRAP interrupt is level and edge triggered. This means that till the acknowledgement, the TRAP must go high and remain high.
• In emergency situations like sudden power failure, it executes an ISR and sends the data from main memory to backup memory.

RST 7.5

• The RST 7.5  can be considered as a maskable interrupt.
• It is a vectored interrupt. The interrupt vector address is 003CH.                                                     
• It has second highest priority.
• It is edge triggered. ie. Input attains at high and no need to retain the high state until it is recognized and acknowledged.


RST 6.5


• The RST 6.5 interrupt is a maskable interrupt.
• It is a vectored interrupt. The interrupt vector address is 0034H.
• It has the third highest priority.
• It is level triggered. ie. Input goes to high and stays high until it is recognized and acknowledged.

RST 5.5


• The RST 5.5 interrupt is a maskable interrupt.
• It is a vectored interrupt. The interrupt vector address is 002CH.
• It has the fourth highest priority.
• It is level triggered. ie. Input goes to high and stays high until it is recognized and acknowledged.

INTR


• INTR is a maskable interrupt.
• It is a non- vectored interrupt. After receiving INTR, the peripheral has to supply the address of
• It has the lowest priority.
• It is a level triggered. ie. Input goes to high and it is necessary to maintain high state until it is recognized and acknowledged.



Process of INTR interrupt


1. With the use of the EI instruction, the interrupt process should be enabled.
2. Whenever an instruction is executed, the 8085 checks for an interrupt signal.
3. If INTR is high, the microprocessor completes current instruction, disables the interrupt and sends INTR signal to the peripheral device.
4. INTR' allows the peripheral device to send an RST instruction through data bus.
5. Upon receiving the INTR signal, the microprocessor saves the memory location of the next instruction on the stack and the program is transferred to ‘call’ location (ISR Call) specified by the RST instruction.
6. Microprocessor executes the ISR.
7. Within the program, In order to enable the further interrupt, ISR must include the ‘EI’ instruction.
8. The RET instruction at the end of the ISR retrieves the return address from the stack and the program is transferred back to main program which was interrupted.

Instructions for Interrupts handling in 8085 microprocessor:


There are four instructions available for interrupts handling. They are,

1. DI (Disable Interrupt)
2. EI (Enable Interrupt)
3. SIM (Set Interrupt Mask)
4. RIM (Read Interrupt Mask)

DI (Disable Interrupt)

This instruction resets the Interrupt Enable Flip-flop inside the microprocessor. All the interrupts except the TRAP are disabled.

EI (Enable Interrupt)

Inside the microprocessor, this instruction sets the Interrupt Enable Flip-flop also all the interrupts are enabled.

SIM (Set Interrupt Mask)

This instruction is used to selectively mask (disable) and unmask (enable) RST 7.5, RST 6.5 and RST 5.5 interrupts. For serial data output, we can use this instruction. The SIM the instruction uses the accumulator contents for masking and unmasking the interrupts.

RIM (Read Interrupt Mask)

This instruction is used to read the status of RST 7.5, RST 6.5 and RST 5.5 interrupts like pending and enable / disable details. This instruction is also used for reading the serial data. When the RIM instruction is given, the microprocessor loads the details into the accumulator.

Summary of 8085 interrupts


Interrupt
Vector address
Priority
Type
TRAP
0024H
1 (highest priority)
Hardware interrupt
Vectored interrupt
Non-maskable interrupt
RST 7.5
003CH
2
Hardware interrupt
Vectored interrupt
Maskable interrupt
RST 6.5
0034H
3
Hardware interrupt
Vectored interrupt
Maskable interrupt
RST 5.5
002CH
4
Hardware interrupt
Vectored interrupt
Maskable interrupt
INTR
-
5(lowest priority)
Hardware interrupt
Non - Vectored interrupt
Maskable interrupt
RST instruction
RST 0 – 0000H
RST 1 – 0008H
RST 2 – 0010H
RST 3 – 0018H
RST 4 – 0020H
RST 5 - 0028H
RST 6 – 0030H
RST 7 – 0038H
-
Software interrupt
Vectored interrupt
Maskable interrupt



Wednesday, 10 July 2019

I/O Mapping in 8085 Microprocessor

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I/O interfacing

There are two methods of interfacing the Input / Output devices with the microprocessor. They are,

1) Memory mapped I/O and
2) I/O mapped I/O.

Memory mapped I/O

In this method the I/O devices are treated like the memory. A part of the memory address space is used for the I/O devices. The memory mapped I/O scheme is shown in figure.
Figure: Memory mapped I/O scheme


• In memory mapped I/O scheme, the same address space is used for both memory and I/O devices.
• The microprocessor uses the sixteen address line A0 – A7 and A8 – A15 for the memory as well as for the I/O devices.
• The I/O devices share the address space with the memory. All the memory related instructions are used for addressing I/O devices also.
• No separate IN and OUT instructions are required in memory mapped I/O scheme.
• IO/𝑀’ pin is not required.



Steps for memory operations (memory read and memory write) :

1. When the memory related instructions like LDA and STA are used, the microprocessor places the 16-bit address on the address bus.
2. 𝑅𝐷’ is activated for read operation and 𝑊𝑅’ is activated for write operation.
Steps for I/O operations (I/O read and I/O write) :
The same steps used for memory operations are used for I/O operations also.

I/O mapped I/O

In this method, I/O devices are treated as I/O devices and memory is treated as memory. Separate address space is used for memory and I/O. The I/O mapped I/O scheme is shown in figure.

Figure: I/O mapped I/O scheme
• In I/O mapped I/O scheme, the microprocessor uses the sixteen address lines A0 – A7 and A8 – A15 for the memory and eight address lines A0 to A7 to identify an input / output device.
• Here, the full address space 0000 – FFFF is used for the memory and a separate address space 00 – FF is used for the I/O devices.
• Hence, the microprocessor can address 65536 (216) memory locations 256 (28) input devices and 256 (28) output devices separately.
• IN and OUT instructions are used to activate the IO/𝑀’ signal.
• When IO/𝑀’ is low, the memory is selected for reading and writing operations.
• When IO/𝑀’ is high, the I/O port is selected for reading and writing operations.

Steps for memory operations (memory read and memory write) :

1. When the memory related instructions like LDA and STA are used, the microprocessor places the 16-bit address on the address bus.
2. The microprocessor makes the IO/𝑀’ linelow.
3. The microprocessor makes the 𝑅𝐷’ low for read operation and 𝑊𝑅’ low for write operation.

Steps for I/O operations (I/O read and I/O write) :

1. When the I/O related instructions like IN and OUT are used, the microprocessor places the 8-bit address on the address bus A0 – A7 as well as A8 – A15.
2. IO/𝑀’ line is made high.
3. The microprocessor makes the 𝑅𝐷’ low for read operation and 𝑊𝑅’ low for write operation.


Timing Diagram of MOV Rd Rs Instruction in 8085

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Timing diagram for MOV Rd, Rs (or MOV r1, r2) instruction

MOV Rd, Rs instruction moves (copies) the contents of the source register (Rs) into the destination register (Rd). It is a single byte instruction. It has only Opcode Fetch machine cycle. Some examples for MOV Rd, Rs instruction:

1. MOV A, B
2. MOV C, L

The time taken by the processor to execute the Opcode Fetch cycle is 4T (T- states). The first 3 T-states are used for fetching the Opcode from memory and the remaining T-state is used for internal operations by the microprocessor. The timing diagram for MOV Rd, Rs (Opcode Fetch machine cycle) is shown in figure. It has 4 T states.
Timing Diagram of MOV Rd Rs Instruction in 8085 Microprocessor

The steps for machine cycle of MOV Rd, Rs instruction are given in table.

S.No
T state
Operation
1
T1
The microprocessor places the higher order 8-bits of the Program Counter on A15 – A8 address bus and the lower order 8-bits of the Program Counter on AD7 – AD0 address / data bus.
2
The microprocessor makes the ALE signal HIGH and at the middle of T1 state, ALE signal goes LOW.
3
The status signals are changed as IO/M'= 0, S1 =1 and S0 = 1. These status signals do not change throughout the OF machine cycle.
4
T2
The microprocessor makes the RD' line LOW to enable memory read (opcode fetch) and increments the Program Counter.
5
The contents on D7 – D0 (i.e. the Opcode) are placed on the address / data bus.
6
T3
The microprocessor transfers the Opcode on the address / data bus to Instruction Register (IR).
7
The microprocessor decodes the instruction.
8
T4
The data in the register Rs (r2) is moved to the register Rd (r1).



Tuesday, 9 July 2019

Arithmetic Instructions in 8085 Microprocessor

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Arithmetic Instructions in 8085 Microprocessor

S.No
Instruction
Example
1.
Add register or memory to accumulator
ADD R
ADD M
ADD B
ADD M
‘Add register or memory to accumulator’ instruction set denotes:-
“The contents of the operand (memory or register) are added to the contents of the accumulator and the result is stored in the accumulator”.
2.
Add register to accumulator with carry
ADC R
ADC M
ADC B
ADC M
“Add register to accumulator with carry” instruction represents:-
The data of the operand (register or memory) and the Carry flag are summed (added) to the datas of the accumulator.
 The result is stored in the accumulator.
3.
Add immediate to accumulator
ADI 8-bit data
ADI 45H
‘Add immediate to accumulator’ instruction denotes:-
The 8-bit data (operand) is added to the data of the accumulator. The result is stored in the accumulator.
4.
Add immediate to accumulator with carry
ACI 8-bit data
ACI 45H
‘Add immediate to accumulator with carry’ instruction represents:-
The Carry flag and the 8-bit data are added to the data of the accumulator .
The result is stored in the accumulator.
5.
Add register pair to H and L registers
DAD Reg. pair
DAD H
‘Add register pair to H and L registers’ instruction represents:-
The 16-bit data of the specified register pair are added to the datas of the HL register .
 The sum is stored in the HL register.
6.
Subtract register or memory from accumulator
SUB R
SUB M
SUB B
SUB M
‘Subtract register or memory from accumulator’ instruction is used for:
The contents of the operand (memory or register ) are subtracted from the contents of the accumulator,.
The result is stored in the accumulator.
7.
Subtract source and borrow from accumulator
SBB R
SBB M
SBB B
SBB M
‘Subtract source and borrow from accumulator’ instruction represents:-
The contents of the operand (register or memory) and the Borrow (carry flag) are subtracted from the contents of the accumulator .
The result is placed in the accumulator.
8.
Subtract immediate from accumulator
SUI 8-bit data
SUI 45H
The instruction ‘Subtract immediate from accumulator’ represents:-
 The 8-bit data (operand) is subtracted from the datas of the accumulator.
The result is stored in the accumulator.
9.
Subtract immediate from accumulator with borrow
SBI 8-bit data
SBI 45H
The instruction ‘Subtract immediate from accumulator with borrow’ represents:-
 The 8-bit data (operand) and the Borrow (carry flag) are subtracted from the contents of the accumulator.
The result is stored in the accumulator.
10.
Increment register or memory by 1
INR R
INR M
INR B
INR M
The instruction ‘Increment register or memory by 1’ represents:-
 The content of the designated register or memory is incremented by 1 and the result is stored in the same place.
11.
Increment register pair by 1
INX Reg. pair
INX B
INX D
INX H


The instruction ‘Increment register pair by 1’ represents:-
The datas of the designated register pair gets incremented by 1.
The result is stored in the same place.
12.
Decrement register or memory by 1
DCR R
DCR M
DCR B
DCR M
‘Decrement register or memory by 1’ instruction represents:-
 The datas of the designated register or memory is decremented by 1 and the result is stored in the same place.
13.
Decrement register pair by 1
DCX Reg. pair
DCX B
DCX D
DCX H
‘Decrement register pair by 1:  DCX Reg. pair ‘ instruction set represents:
 The datas of the designated register pair gets decremented by 1.
 The result is stored in the same place.
14.
Decimal adjust accumulator
DAA
DAA
‘Decimal adjust accumulator’ instruction set represents:-
DAA The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD) digits.
 If AC flag is set  or the value of the low-order 4-bits in the accumulator is more than 9, the instruction adds 6 to the low-order four bits.   
 If the value of the high-order 4-bits in the accumulator is more than 9 or the Carry flag is set, the instruction adds 6 to the high-order four bits.