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Thursday, 24 October 2019

Pinout of 8086 Microprocessor

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Pinout of 8086 Microprocessor is shown in figure below.
8086 can operate in two multimode of operations.

(1) Minimum Mode

8086 Minimum Mode

(2) Maximum Mode
8086 Maximum Mode
At a time, 8086 processor can act as a minimum mode or maximum mode.
MN/MX’ Pin (Pin no: 33) determines the mode of 8086 processor.

When MN/MX’ is in high state, 8086 processor operates at minimum mode.
When MN/MX’ is in low state, 8086 processor operates at maximum mode of operation.

In maximum mode of operation, 8086 processor will act as a Multiprocessor. In uniprocessor system, 8086 processor will do all the operations. In multiprocessor system, more than one processor is connected.

Note: In order to perform the exponential operation, another processor (co processor) is connected in parallel with 8086 (main) processor.

Co Processor of 8086 is 8087: Co Processor is used to perform floating point operation, exponential operations etc.

CLK (Clock):

Clock defines the speed of the processor.
In 8086 Processor, external clock is same as the internal clock.
In 8085 Processor, internal clock is half of the external clock.


NMI and INTL:

8086 processor has two hardware interrupts. In 8086 processor, two pins are provided for interrupts and these are called hardware interrupts. They are NMI and INTR.

INTR – Interrupt Request Signal
NMI – Non Maskable Interrupts

In Non Maskable Interrupts, the programmer cannot change the priority of interrupt. But in maskable interrupts, programmer can change the priority of interrupts.

RD’ is the read signal (Memory read or I/O read).
WR’ is write signal (Memory write or I/O write)

When RD’ is low, that operation is read operation and when WR’ is low, that operation is Write Operation. When M/Io’ is in high state, the operation is I/O operation. When M/Io’ is in high state, the operation is I/O operation. When M/ Io’ is at low state, that operation is memory related.

M/ Io
RD’
WR’
Operation
1
0
1
Memory Read
1
1
0
Memory Write
0
0
1
I/O read
0
1
0
I/O write

HOLD and HLDA:

HOLD is a request signal send by the peripheral devices to the microprocessor to release the control of the system buses.

HLDA is a hold acknowledgement signal; send by the processor to the peripheral devices.

ALE (Address Latch Enable):

ALE is used to demultiplex address/data bus. When ALE is in high state, multiplex bus act as a address bus. When, ALE is in low state, MUX act as a bus.
INTA’ is the interrupt acknowledgement signal.
DT/R’ is the data transmit/receive signal.

DEN’ (Data Enable)

When DEN’ is enabled, that data bus contains a valid data.

RQ’/GT0 and RQ’/ GT1

RQ’/GT0 and RQ’/ GT1 are the bus request/bus grand signal, send by the peripheral devices to the microprocessor.

QS0 and QS1

QS0 and QS1 gives the status of the Q-register.

READY

When READY signal is in low state, the processor will act in the slower state. When READY signal is in high state, the processor can go to the next state.

TEST’

When READY Signal is in low state, TEST’ is in high state.
When TEST’ is in low state, READY is in high state, then only the processor can perform the next state task.

Status Signal during memory segment access

Status Signal
Segment Register
S4
S3
0
0
Extra Segment
0
1
Stack Segment
1
0
Code or No Segment
1
1
Data Segment

Queue Status

Queue Status
Queue Operation
QS1
QS0
0
0
No Operation
0
1
First byte of an opcode from queue
1
0
Empty the Queue
1
1
Subsequent byte from Queue

Status Signal during various machine operation

Status Signal
Machine Cycle
S2
S1
S0
0
0
0
Interrupt acknowledgement
0
0
1
Read I/O Port
0
1
0
Write I/O Port
0
1
1
Halt
1
0
0
Code Access
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
Passive/Inactive

Flags in 8086 Processor:

In 8086, flags are classified into Directional Flag, Conditional Flag and Control Flag.
Flag register keeps the status of Operation.

1. Zero Flag: If the result of an operation is zero, then the zero flag will set and if the result is non zero, then the zero flag will resets.

2. Carry Flag: If the result of an operation contains carry, then the carry flag will set and otherwise it will reset.

3. Overflow Flag: If the result of an operation exceeds the capacity of the memory location, overflow occurs. When overflow occurs, the overflow register will set, otherwise it will resets.

4. Parity Flag: The parity flag will set, if the result is even parity and the parity flag will resets, if the result is odd parity.

5. Sign Flag: If the number is negative, then the sign flag will set  and if the number is positive, sign flag will resets.

6. Auxiliary Carry Flag: If there is carry in the lower byte, the auxiliary flag will set, otherwise it will resets.

7. Directional Flag: When the processor is in auto decrement mode of operation, directional flag will set and when the processor is in auto increment mode, directional flag will reset.

8. Interrupt Flag: At the time of interrupt operation, interrupt flag will set and otherwise it will reset.

9. Single Step Flag: When the processor is in single step operation, single step flag will set, otherwise it will reset.



Wednesday, 23 October 2019

Microprocessor based System Block Diagram

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Basic Functional Blocks of a Microprocessor 

Register Array:

Register array is group of registers. Register array contains general purpose registers and special purpose registers. It is used for temporary storage of data.

Instruction Decoding Unit:

Instruction decoding unit decodes the instruction. In order to execute (perform) the operation, all data should be decoded. The processor cannot perform the execution, if data are not decoded.

ALU :

All the arithmetic and logic operations are performed with respect to ALU. The execution is taken inside the ALU.

Timing and Control Unit:

In order to perform all the operations, some predefined timing period is required. That is, with respect to the time period, the processor will works. The control unit releases the control signal. Control Signal provides control to both the processor and to the peripheral devices.


Flag Register:

Flag register is very near to ALU. “Flag register keeps the status of the last operation”. That is, by the help of flag register, the processor can understand the status of the last operation. Processor cannot access the data directly from the flag register.

In 8086 Processor, all the general purpose and special purpose registers except deoding registers are 16 bit registers.

Program Counter (PC)/ Instruction Pointer (IP):

Instruction pointer will store the address of the next instruction to be executed. That is, the address of the next instruction to be executed is stored in PC.

In 8086, PC is a 16 bit register. This means that, in 8086, 20 address lines are used. So the 8086 has 16-bit registers and 20 address lines.

In 8085 Processor, 8 bit registers and 16 number of address lines are used.

Total Memory that can be accessed by any processor = 2number of address lines.

In 8085 Processor, Total Memory that can be accessed = 216 bytes = 64 KB

In 8086 Processor, Total Memory that can be accessed = 220 bytes = 1 MB

Note: In 8086 processor, each memory   can save only 8 bit data. So in order to store 16-bit data, two consecutive memory locations are needed. 8086 Processor is a 40 Pin Processor.
Memories are classified into

(a) Even Memory
(b) Odd Memory

Microprocessor based System:

Microprocessor based System Block Diagram is shown below.

In order to perform every operation, the processor should require some peripheral (supporting) devices such as memory, input base, output base etc. Microprocessor is a parallel communicating device.

8086 processor works under a set of instructions.

RAM – used for Read and Write Operations
EPROM – Erasable Programmable ROM

In a processor, Data and control bus are bidirectional, but address bus is unidirectional.

In 8086 processor, 16 address lines and 20 data lines are Multiplexers. At other times, it acts as data bus. In 8086 processor, first 16 data lines are multiplexed with first 16 address lines. A multiplexer cannot perform any operation directly.


Tuesday, 22 October 2019

Internal Block Diagram of 8086 Microprocessor

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The Internal Block Diagram of 8086 Microprocessor is shown below.


The functional block diagram of 8086 is divided into two functional units.

 (1) Bus Interface Unit and (2) Execution Unit

They are explained below.

(1) Bus Interface Unit:

Bus Interface Unit is a gate (enhance) interface between peripheral devices and Processor. Through the bus interface only, processor can send and receive data. The bus interface unit contains

(a) Instruction Queue
(b) Segment Registers
(c) Instruction Pointers

(a) Instruction Queue

In 8086 Processor, instruction queue is a 6 byte register used to store permanent data from the Input/Output (I/O) devices or processor. The queue operates in the principle of First In First Out (FIFO) principle. i.e., the first data is fetched and that data will be taken out firstly.

(b) Segment Register:

In 8086 Processor, there are four segment registers. They are

ES – Extra Segment
CS – Code Segment
DS – Data Segment
SS – Stack Segment

The maximum memory access of 8086 processor is 1 MB. Each segment has some predefined functions.


In 8086 processor, each segment has a capacity of 64 KB. So the four segments will store 256 KB of memory locations. The remaining memory locations are free and in these locations, user can perform any other processes. These four segment registers will keep the base address of the corresponding segment.

(c) Instruction Pointer (IP):

Instruction pointer will give the next address of the instruction to be executed. Instruction Point cannot be used for other purposes.

(2) Execution Unit:

The execution unit contains

(a) Control Unit
(b) Instruction Decoders
(c) ALU
(d) General Purpose Registers
(e) Flag Registers

Address Generation:

The I/O processor can receive data from the memory only, if that data should goes out through the address generation.

General Purpose Registers:

AX, BX, CX, DX, SP, BP, SI, DI are General Purpose Registers.

1. AX register (Accumulator):

AX register can save 16 bit data only.

2. BX register:

BX register is the base register. It is used to save the base data (value).

3. CX register:

CX register is code register (Count Register)

4. DX Register:

DX register is data register. DX register is used to store datas.

5. SP (Stack Pointer):

Stack Pointer keeps the top of the stack. The stack pointer operates in the principle of Last In First Out (LIFO). Since one location can store only 8 bit data, in order to store a 16 bit data, two memory locations are needed. So the stack pointer will decreased by two memory locations, if a data is taken.

6. BP (Base Pointer):

Base pointer is used to store the base address of the memory or stack.

7. SI (Source Index):

Source Index is used to hold the index value of source operand for string instructions.

8. DI (Destination Index):

DI is used to hold the index value of destination operand for string instructions.
General purpose registers are used for holding data, intermediate results, counters, mode of addressing and also for storing effective address.

Flag Registers:

The three control flags are,
1. Trap Flag (TF)
2. Interrupt flag (IF)
3. Direction Flag (DF)

Instruction Format,


  15           14          13       12      11      10          9          8          7          6           5          4        3         2          1         0
U
U
U
U
CF
DF
IF
TF
SF
ZF
U
AF
U
PF
V
CF


Symbolic Representation,