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Wednesday, 30 October 2019

Forward Bias and Reverse Bias Diagram

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P-N JUNCTION :

When P and N-type materials are joined, a thin junction formed 8 is called P-N junction. There are two methods of forming P-N junction. In the grown junction a single crystal is obtained from a melt which at first contains impurities of either the P or N - type. In the middle of the growth process, impurities of the opposite kind are added to the melt, so that the remainder of the crystal abruptly grows into the opposite type. In the second method, junction is by fusing together the two metals to form an alloy and is known as fused P-N junction. In this method a small disc of P-type material (Indium) is placed on a somewhat larger flat plate of N-type silicon. The materials are held in a graphite holder and heated to temperature of about 600°C. The indium disc melts at about 155°C. As the temperature rises further it dissolves away some of the silicon beneath it. In the molten region the indium first neutralizes the N-type impurities in the silicon and then leaves an excess of P-type impurities. A P-N junction is thus formed between this P-region and the remainder of the N-type silicon melts (See Diagram).

Forward Bias P-N Junction :

When an external voltage is applied across the two materials a flow of current results if the positive terminal and negative terminal of the voltage source are connected to the extreme ends of P and N materials respectively. Voltage applied in this way is called forward biasing the P-N junction (See Diagram).

This arrangement permits flow of current across the P-N junction. The holes are repelled by the positive battery terminal and electrons by the negative battery terminal with the result that both holes and electrons will be driven towards the junction where they will recombine. As long as the battery voltage is applied large current flows. In other words forward biasing lowers the potential barrier across the depletion layer thereby allowing more current to flow across the junction. The volt-amp characteristics of forward biased P-N junction are shown in Figure.
Reverse Bias P-N Junction :

If the positive of the supply voltage is connected to N type and the negative of the battery to P-type it is said to be connected as Reversed biased (See Diagram).

In this case, the holes are attracted by the negative battery terminal and electrons by the positive battery terminal, so that both holes and electrons more away from the junction. Since, there is no recombination of electron hole pairs. It increases the potential barrier at the junction thereby allowing very little current to flow through the junction. The volt-amp characteristics of Reversed biased P-N junction is given in Figure.



Sunday, 27 October 2019

Properties of N type and P type Semi Conductors

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N-type Semi Conductors :

Impurities like Arsenic and Antimony have five valence electrons and are called the pentavalent impurity. When a pentavalent impurity is added to the intrinsic semi conductor, only four of its five valence electrons lock into the covalent bond formation of the atomic structure, and the fifth electron of the impurity is free to move through the crystal. As long as the impurity atoms are far apart the single electron behaves as an isolated atom. The energy of this electron is just less than that of the conduction band of Germanium and it may easily be excited by thermal energy into the conduction band and so takes part in conduction. The conduction is mainly by the electrons in the conduction band. The lattice of the N-type of semi conductor is shown in Figure.


P-type Semi Conductor:

When materials like Aluminium, Boron, Indium etc., which has three valence electrons are added to intrinsic semiconductors is small quantities, the impurity atom replaces a Germanium (or Silicon) atom in the crystal lattice resulting in a positive hole available for electrons. Impurities with three valence electrons called trivalent group, and the impurities are called acceptor. The energy of the vacant level is just above the filled valence band of Germanium and an electron may be easily excited thermally into the vacancy leaving a positive hole in the valence band. Electrical conduction now takes place due to positive holes and we get P-type of semiconductor. In P-type materials holes are the majority carriers and electrons are the minority carriers. The crystal lattice of a P-type semiconductor is shown in figure above.


Properties of N type and P type Semi Conductors:

Electrical Characteristics:

Electrical Characteristics of P and N type semi conductors are given in table below.


N - Type
P - Type
Impurities
Elements of Group V
Phosphorous (P)
At. No. 15, At.Wt 30.97
Arsenic (As)
At. No. 33, At.Wt 74.92
Antimony (Sb)
At. No. 51, At.Wt 121.75
Bismuth (Bi)
At. No. 83, At.Wt 208.99
Elements of Group III
Boron (B)
At. No. 5, At.Wt 10.81
Aluminium (Al)
At. No. 13, At.Wt 26.98
Gallium (Ga)
At. No. 31, At.Wt 69.72
Indium (In)
At. No. 49, At.Wt 114.82
Function of Impurities
Donor
Acceptor
Valence Impurities
5
3
Nature of Majority Carriers
Electrons
Holes
Band in which conduction takes place
Conduction Band
Valence Band
Energy gap
0.01 ev (Germanium)
0.05 ev (Silicon)
0.01 ev (Germanium)
0.045 ev (Silicon)

Functional Characteristics:

The functional characteristics of Semi Conductors are given in below Table.

Substances
Melting Point oC
Forbidden Energy gap
eV
Electron mobility cm2/volt-sec
Hole mobility cm2/ volt-sec
B
2300
1.1
10
10
Si
1420
1.11
1200
250
Ge
940
0.72
3600
1700
Te
452
0.36
1700
1200
Hg Te
670
0.2
10,000
100
B2 Te3
585
0.2
600
150
Mg2 Sb
778
0.36
200
150
PbSo
1065
0.5
1400
1400
PbS
1114
1.2
650
800
Cd Te
1045
1.45
450
100



Saturday, 26 October 2019

Resistivity of Semiconductor

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The resistivity of semi conductor mostly depends on temperature and hence classifying a material as semi conductor basing on resistivity alone will not be correct. At very low temperatures near to the liquid helium the resistivity of the semi conductor may be equal to that of insulator. Therefore a better way is to consider the criterion from the graph given in Figure which is drawn for resistivity verses temperature for three typical semi conductor material. In all these cases the semiconductor exhibits a negative temperature co-efficient of resistivity atleast over a part of the temperature range. Since the resistivity is a function of temperature co-efficient of resistivity it can be written as

α1 = dρ/dT

For semi conductor the value is negative where

ρ is the resistivity of the material
T is Temperature
α1 – temperature co-efficient of resistivity
Resistivity vs Temperature
The valence electrons are not attached to individual atoms but are free to move in all directions among the atoms. These electrons are caIled conduction electrons and form 'free electron cloud' or 'free -electron gas' or the 'fermi gas'. When external field is applied to the metal, the free electron motion becomes directed. This type of motion is known a 'drift'.  The drift velocity is given by,
v = μe E

where

v - electron drift velocity
μe = electron mobility
E = applied electrical field.


The electric current flowing in any conductor is given by the amount of charge which flows in one second across any place of the conductor. The total number of electrons which cross any plane of cross section A in one second is equal to n (v x A) where, n is the free electrons per unit volume of the conductor i.e., electron density.

Charge carried by the electrons

I = e n v A
But v = μe A
Therefore, I = e n A μe E
The applied field E = v/l
Therefore, I = e n A μe v/l
But, R = ρl/A
R = v/I = l/A[1/ ne μe]
Therefore ρ = (1/ ne μe) Ω-m
and Conductivity σ = 1/ ρ = ne μe mho/m

Therefore in a semi conductor, charged carriers are both holes as well as electrons whereas in metals electrons are the only charged carriers.

Factors Affecting Resistivity of Semi Conductors

The resistivity of semi conductor are affected by the following factors :

(a) Impurities : The behaviour of a semiconductor mostly depends on the degree and type of impurity in crystal. Increase in conductivity is smaller for low values of impurities as compared to intrinsic type of semiconductor. For high values of impurity it behaves as an intrinsic semi conductor. Figure shows the curves on semi log paper showing the resistivities of semiconductor versus temperature for different amount of N - type impurity.

(b) Temperature : The temperature limit of semi conductor is set up by the band gap of the material. At higher temperatures, it behaves as an intrinsic semi conductor. For Germanium and Silicon the higher limits are 100oC and 300oC. At lower temperature of – 200oC, they act as insulator. The impurity activation energies also increase band gap of the parent crystal resulting in unsatisfactory operational results at room temperature.

(c) Illumination : Light contains bundles of electromagnetic energy and the amount of energy in bundle depends upon the frequency of light. The resistivity of semi conductor is less in light and more in darkness. The property is used in Photo conducting cells.

(d) Electric field : The resistance of semi conductor greatly depends upon the magnitude of electric field. The current does not follow ohm's law and increases rapidly than the voltage. This property has been made use of in Transistors.

(e) Voltage : The resistance of semi conductor varies with the applied voltage. This property is used in varistors.


Thursday, 24 October 2019

Pinout of 8086 Microprocessor

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Pinout of 8086 Microprocessor is shown in figure below.
8086 can operate in two multimode of operations.

(1) Minimum Mode

8086 Minimum Mode

(2) Maximum Mode
8086 Maximum Mode
At a time, 8086 processor can act as a minimum mode or maximum mode.
MN/MX’ Pin (Pin no: 33) determines the mode of 8086 processor.

When MN/MX’ is in high state, 8086 processor operates at minimum mode.
When MN/MX’ is in low state, 8086 processor operates at maximum mode of operation.

In maximum mode of operation, 8086 processor will act as a Multiprocessor. In uniprocessor system, 8086 processor will do all the operations. In multiprocessor system, more than one processor is connected.

Note: In order to perform the exponential operation, another processor (co processor) is connected in parallel with 8086 (main) processor.

Co Processor of 8086 is 8087: Co Processor is used to perform floating point operation, exponential operations etc.

CLK (Clock):

Clock defines the speed of the processor.
In 8086 Processor, external clock is same as the internal clock.
In 8085 Processor, internal clock is half of the external clock.


NMI and INTL:

8086 processor has two hardware interrupts. In 8086 processor, two pins are provided for interrupts and these are called hardware interrupts. They are NMI and INTR.

INTR – Interrupt Request Signal
NMI – Non Maskable Interrupts

In Non Maskable Interrupts, the programmer cannot change the priority of interrupt. But in maskable interrupts, programmer can change the priority of interrupts.

RD’ is the read signal (Memory read or I/O read).
WR’ is write signal (Memory write or I/O write)

When RD’ is low, that operation is read operation and when WR’ is low, that operation is Write Operation. When M/Io’ is in high state, the operation is I/O operation. When M/Io’ is in high state, the operation is I/O operation. When M/ Io’ is at low state, that operation is memory related.

M/ Io
RD’
WR’
Operation
1
0
1
Memory Read
1
1
0
Memory Write
0
0
1
I/O read
0
1
0
I/O write

HOLD and HLDA:

HOLD is a request signal send by the peripheral devices to the microprocessor to release the control of the system buses.

HLDA is a hold acknowledgement signal; send by the processor to the peripheral devices.

ALE (Address Latch Enable):

ALE is used to demultiplex address/data bus. When ALE is in high state, multiplex bus act as a address bus. When, ALE is in low state, MUX act as a bus.
INTA’ is the interrupt acknowledgement signal.
DT/R’ is the data transmit/receive signal.

DEN’ (Data Enable)

When DEN’ is enabled, that data bus contains a valid data.

RQ’/GT0 and RQ’/ GT1

RQ’/GT0 and RQ’/ GT1 are the bus request/bus grand signal, send by the peripheral devices to the microprocessor.

QS0 and QS1

QS0 and QS1 gives the status of the Q-register.

READY

When READY signal is in low state, the processor will act in the slower state. When READY signal is in high state, the processor can go to the next state.

TEST’

When READY Signal is in low state, TEST’ is in high state.
When TEST’ is in low state, READY is in high state, then only the processor can perform the next state task.

Status Signal during memory segment access

Status Signal
Segment Register
S4
S3
0
0
Extra Segment
0
1
Stack Segment
1
0
Code or No Segment
1
1
Data Segment

Queue Status

Queue Status
Queue Operation
QS1
QS0
0
0
No Operation
0
1
First byte of an opcode from queue
1
0
Empty the Queue
1
1
Subsequent byte from Queue

Status Signal during various machine operation

Status Signal
Machine Cycle
S2
S1
S0
0
0
0
Interrupt acknowledgement
0
0
1
Read I/O Port
0
1
0
Write I/O Port
0
1
1
Halt
1
0
0
Code Access
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
Passive/Inactive

Flags in 8086 Processor:

In 8086, flags are classified into Directional Flag, Conditional Flag and Control Flag.
Flag register keeps the status of Operation.

1. Zero Flag: If the result of an operation is zero, then the zero flag will set and if the result is non zero, then the zero flag will resets.

2. Carry Flag: If the result of an operation contains carry, then the carry flag will set and otherwise it will reset.

3. Overflow Flag: If the result of an operation exceeds the capacity of the memory location, overflow occurs. When overflow occurs, the overflow register will set, otherwise it will resets.

4. Parity Flag: The parity flag will set, if the result is even parity and the parity flag will resets, if the result is odd parity.

5. Sign Flag: If the number is negative, then the sign flag will set  and if the number is positive, sign flag will resets.

6. Auxiliary Carry Flag: If there is carry in the lower byte, the auxiliary flag will set, otherwise it will resets.

7. Directional Flag: When the processor is in auto decrement mode of operation, directional flag will set and when the processor is in auto increment mode, directional flag will reset.

8. Interrupt Flag: At the time of interrupt operation, interrupt flag will set and otherwise it will reset.

9. Single Step Flag: When the processor is in single step operation, single step flag will set, otherwise it will reset.