THE TRI-STATE LOGIC GATE
Usually, logic gates have only two states of operation, viz., 0 and 1. In certain applications, we require the use of a third state. This state is known as the high-impedance (high-Z) state. The logic gate with three states of operation is known as a tri-state logic gate. They are used as buffer gates for isolation purposes. Figure 3.17 shows a typical tri-state logic gate, which is a modification of the two-input TTL NAND gate with the addition of diodes D1 and D2 and an inverter gate (in Fig. 3.17, we have not included transistor T1 of the conventional TTL NAND).
Usually, logic gates have only two states of operation, viz., 0 and 1. In certain applications, we require the use of a third state. This state is known as the high-impedance (high-Z) state. The logic gate with three states of operation is known as a tri-state logic gate. They are used as buffer gates for isolation purposes. Figure 3.17 shows a typical tri-state logic gate, which is a modification of the two-input TTL NAND gate with the addition of diodes D1 and D2 and an inverter gate (in Fig. 3.17, we have not included transistor T1 of the conventional TTL NAND).
Let, initially, the chip-select enable/disable terminal CS = 0. This makes CS′ = 1, which reverse biases the diodes D1 and D2. In this condition, the circuit behaves as a normal NAND gate.
Now, let CS = 1, so that CS′ = 0. Then diodes D1 and D2 become forward biased and we find that the base and collector of T2 are grounded through the ON-diodes. This makes both T3 and T4 to be in the OFF-state and the impedance of the output stage becomes very high. This is the third high-Z state. In such a state, several gates can be ORed together.
Application of Tri State Buffer
Practical application of the tri-state buffer is shown in Fig. 3.18. This is mainly used in bus-line systems of computer chips. In Fig. 3.18, bus lines, represented by thick lines, are used to transfer data from one register to another register. As shown, data from register A can be transferred to any other register connected to the common bus line. From the figure, we find that register B also is connected to the bus line. Register A can be enabled or disabled by using the CS terminal. Those tri-state buffers which we want to operate are enabled and those which we do not want to operate are disabled. Suppose the tri-state gates associated with registers A and B are enabled and some others (not shown in the figure) are disabled. Then data will flow from A to B through the common bus line, but it will not flow into those gates that are disabled.
Can you please suggest the reader for the logic families
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