Theme images by Storman. Powered by Blogger.

Open Collector TTL NAND Gate

If transistor T3 is removed from the totem-pole configuration, we get an open-collector TTL gate. Figure 3.15 shows an open-collector TTL NAND gate. This can be converted into a NAND gate by connecting a pull-up resistor across the output terminals P and Q

The Wired-AND (or Wired-OR) Gate

The open collector gate is used for producing the Wired-AND (or Wired-OR) connection. As shown in Fig. 3.16(a), several NAND gates can be ANDed together using an open-collector TTL gate. This results in the Wired-AND (because the ANDing is obtained through the interconnection of the outputs) logic expression:

Z =(AB)¢(CD)¢(EF)¢                                     (3.1)

Figure 3.16(b) shows the shorting of the collector terminals of the output transistors of the three respective NAND gates to form ANDing operation. However, this can also be recognized as a Wired-OR connection because the output Z in Fig. 3.16(b) can be written in the form

Z = (AB + CD + EF)¢                          (3.2)

Equation (3.2) shows that the circuit shown in Fig. 3.16(a) performs the NORing of several AND gates. Now, applying De-Morgan’s laws on Eq. (3.2), we obtain

Z =(AB)¢(CD)¢(EF)¢ = (AB + CD + EF)¢                             (3.3)

Inspection of Eq. (3.3) reveals that the output Z shows the ANDing of several NAND gates, which is also equivalent to NORing of several AND gates. The value of the pull-up resistor Rpull-up is determined by the maximum value of the collector current permissible through each of the output transistors