Noise Margin and Noise Immunity in logic families

Noise Margin in Logic Families

Figure 3.12 shows a TTL NAND gate N₁ driving another TTL NAND gate N₂. Assume that N₁ is in the ON-state with V_OLmax = 0.4 V and N₂ is in the OFF-state with V_ILmax = 0.8 V. We find that in between N₁ and N₂, a maximum noise voltage of +0.4 V may be introduced without producing a triggering of N₂. This means that the gates working in a noisy atmosphere can tolerate noise voltages of up to + 0.4 V.  Similarly, if N₁ is OFF with the output voltage V_OH = 2.4 V, and N₂ is ON with V_IH = 2.0 V, the noise margin will be 2.4 − 2.0 = 0.4 V. In this case, the noise voltage is negative, as we have to subtract it from the input.

The margin in the noise voltage levels as explained above is called as the noise margin of the gate. Typical value of noise margin of TTL gates is 0.4 V. Thus from definition, we find:

+V_nm  = V_ILmax – V_OLmax

 ‒V_nm  = V_OHmax – V_IHmax

In the case of CMOS, the noise, we find that noise margin is quite high, and hence they highly suitable for working in industrial atmospheres. For CMOS gates, V_IH = 7 to 10 volts. V_IL = 0 to 3 volts, V_OH = V_DD, and V_OL = 0 to 0.05 volt. Hence, V_{nm( CMOS)} = V_DD.

Noise Immunity in Logic Families

Noise immunity of a TTL gate represents its ability to withstand the interference of noise in its smooth operation. This is a term derived from the theory of noise voltages. Noise margins of TTL gates were found to be equal to ±0.4 volt. We then say that these gates are immune to noise up to ±0.4 V. Noise immunity of CMOS gates is equal to V_DD.

Propagation Delay t_P

Propagation delay is defined as the time taken by a signal to get transmitted through an IC gate. Typical value of t_P lies in the range of a few nanoseconds.