The input-output characteristic of a TTL inverter shows the variation of its output voltage Vo with respect to the variations in its input voltage Vi. Figure 3.7 shows an experimental setup for plotting the characteristics of a two-input 7400 NAND gate IC whose input terminals are shorted together to form an inverter (NOT) gate. For plotting the inverter characteristic, we vary the input voltage from 0 V to +5 V in steps of 0.1 V and note the corresponding values of output voltage.
To plot the characteristic, as stated before, we vary input voltage Vi from 0 to 5 V in steps of, say, 0.1 V and note the corresponding output voltage Vo. First, let Vi = 0 V. This situation is shown in Fig. 3.9. We find that when Vi = 0, transistor T1 starts conducting and its base current IB1 starts flowing, as indicated in the figure. To find IB1, we first find VRB1 across the 4-kΩ resistor RRB1 as:
where VBES3 = base-emitter saturation voltage of T3, and VD = voltage drop across the diode D. There may be slight variations in this value of 3.4 V. For example, VBES3 may vary from 0.7 to 0.8 V, and VD may vary from 0.6 to 0.8 V. These suggest that Vo may lie in between 3.4 V and 3.6 V. Thus, we find that for low input voltages (Vi = 0),output Z =1
Figure 3.8(a) shows the ideal characteristic of an inverter. In Fig. 3.8(a), we find that when Vi = 0 V, Vo = +5 V and when Vi = +5 V, Vo = 0 V. This means that, ideally, the transition from 0-to-1, and 1-to-0 should occur in zero time. Thus we expect an ideal inverter characteristic to have sharp vertical edges, as shown in Fig. 3.8(a). However, the practical inverter characteristic shown in Fig. 3.8(b) can be seen to differ greatly from the ideal characteristic.
VRB1 = VCC − VBES1 = 5 – 0.8 = 4.2 V
where VBES1 = base-emitter saturation voltage of T1. Therefore, base current of T1
IB1 = 4.2 V/4 kΩ = 1.05 mA
This base current turns T1 ON and its collector-emitter voltage drops to the saturation value of VCES1 = 0.2 V. This means that voltage at the base of T2 with respect to the ground, VB2 = VCES1 = 0.2 V, as shown in Fig. 3.9. This keeps T2 OFF and we find that its collector voltage VC2 = +VCC = VB3 (base to ground voltage of T3 of and turns it ON. From the diagram, the output voltage at point Z (indicated by line AB in Fig. 3.8(b) is given by
Z = Vo = VCC −VBES3 − VD = 5 − 0.8 − 0.8 = 3.4 V ≡ logic 1
Now consider the input being slowly increased in steps of 0.1 V each from its initial value of 0 V. We find that Vo remains constant at 3.4 V up to about Vi = 0.6 V. This is because up to 0.6 V,
VB2 = Vi (= 0 to 0.6 V) + VCES1 (= 0.2 V)
Using this relation, we find that at Vi = 0.6 V, VB2 (= 0.6 + 0.2) = 0.8 V, as shown in Fig. 3.10. Let this voltage be divided between VBE2 and VRE2, where VBE2 = base-emitter voltage of T2, and VRE2
= voltage drop across the 1-kΩ emitter resistor of T2, as shown in Fig. 3.10. Also, let VBE2 = 0.5 V, and VRE2 = 0.3 V. When VBE2 = 0.5 V (cut-in voltage), T2 enters into its conduction mode and begins to act as an amplifier. Since RE2 is not bypassed, T2 will act as a current-series feed back amplifier having a negative voltage gain of AV2 = ‒RC2/RE2 = ‒1.6 kΩ/1 kΩ = ‒1.6.
As T2 begins to conduct, its collector current IC2 starts flowing through RC2 and RE2. At this time, we still have T3 ON and T4 OFF. Therefore, when IC2 flows through RC2 to develop a potential drop of VRC2 = IC2RC2. This drop in turn reduces the potential at C2 (collector of T2) by this
value from its initial value of VCC = 5 V. When VC2 = 5 − IC2RC2, output voltage Vo also will drop by the same amount from 3.4 V. Therefore, we find
Vo = 3.4 − IC2RC2
This equation shows that as IC2 is increases, Vo decreases linearly (because amplification is a linear operation) from 3.4 V with a slope of −1.6 (equal to the voltage gain of the current-series feedback amplifier T2). This state will continue up to about Vi =1.2 V. When Vi = 1.2 V, we find that base current IB1 of T1 is given by
IB1 = (VCC − VBE1 − Vi)/RB1 = (5 − 0.6 − 1.2) V/4 kΩ = 0.8 mA
The computations given above show that T1 is still in its active region. For Vi = 1.2 V, the voltage levels are as shown in Fig. 3.11. With VBE2 = 0.8 V, we find T2 to be in saturation, and its collector-emitter voltage VCE2 = 0.2 V. Just before this condition, we find that T2 is still acting as a current-series feedback amplifier, and with an input voltage of 0.6 V its collector voltage VC2 ≈ –1.6 × 0.6 = –0.96 V (these values may change slightly). Then the output voltage
Vo = 3.4 – 0.96 = 2.44 V
This is indicated as point C in Fig. 3.8(b). We also notice that, since VRE2 = 0.6 V, VBE4 = 0.6 V and this makes T4 to start conducting.
Now, if the input voltage is increased from 1.2 V to, say, 1.3 V, we find that VRE2 becomes greater than 0.6 V and T4 enters into saturation. With T4 in the conducting state, we have its output voltage Vo = Z = 0.2 V. This drop in output voltage Vo from 2.4 V (corresponding to Vi = 1.2 V) to 0.2 V, (corresponding to Vi = 1.3 V) is very sharp, and has a slope ≈ ‒(2.44 – 0.2)/0.1 = 22.4. This is indicated by the line segment CD in Fig. 3.8(b).
We observe that, if the input is increased from 1.3 V to +5 V (the maximum permissible value of VCC for TTL gates), the output voltage is found to remain constant at 0.2 V, which ensures that the TTL inverter output is at logic 0. This is indicated by segment DE in Fig. 3.8(b).
Turn-On and Turn-Off Input and Output Voltages
1. VIL: This is the voltage recognized by a TTL gate at its input to keep its output at logic 1, (i.e., transistor T4 is in the OFF-state). Typically, VIL ranges from 0 to 0.8 volt.
2. VIH: This is the input voltage required to produce a change in the output from logic 1 to logic 0. VIH lies between 2 and 5 volts.
3. VOL: This is the output voltage of a TTL gate recognized as logic 0 (i.e., T4 in the ON-state). VOL lies between 0.1 and 0.4 volt.
4. VOH: This is the output voltage of the TTL gate recognized as logic 1. VOH varies between 2.4 and 3.6 volts.