Pass Transistor Logic Working

Transmission gates can be used to construct logic gates, since they can also be used as digital switches. In this mode of operation, the gates act as pass-transistors and the logic using pass-transistors as logic elements is called as pass-transistor logicPass Transistor Logic Working is given below.

Pass Transistor Logic for XOR Gate

Figure 3.41 shows a PTL EXOR gate. The working of the circuit may be explained as follows. As shown, the inputs to the pass-transistor gates (PTGs) 1 and 2 are A and A', respectively, and the control-gate voltages are B and B', respectively.

      Let initially A = B = 0. Then A' = B' = 1; this makes TG1 enabled and TG2 disabled. Under these conditions input A (= 0) gets transmitted through TG1 to the output, which makes the output Z = 0. Similarly, if A = B = 1, then A' = B' = 0 and TG2 becomes enabled with TG1 disabled. Under this situation, A' (= 0) gets transmitted through TG2 to make the output Z = 0 again.

      Now, let A = 1 and B = 0. Then A' = 0 and B' = 1. This makes TG1 enabled and TG2 disabled, and A (= 1) gets transmitted through TG1 to make Z= 1. Similarly, when A = 0 and B = 1, TG1 is disabled and TG2 is enabled. Then B (= 1) gets transmitted through TG2 making the output Z= 1 again. It can be seen that the four operations explained above suggest that Fig. 3.41 is an EXOR gate.

We know that a conventional CMOS EXOR gate requires twelve transistors for its implementation. However, the TG logic EXOR gate requires only eight transistors (four for the two inverters to form the A' and B' inputs, and four for the two TGs). Hence, pass-transistor logic gates are much smaller in chip area than their CMOS counterparts.
                                                                            
Pass Transistor Logic for Multiplexer

Figure 3.42 shows a 2 ×1 multiplexer using TGs. Here, the inputs A and B are applied to TG1 and TG2, respectively. The control inputs are C and C', respectively, as shown. Let C = 0, then C' = 1 and TG1 is enabled now; this makes A to be selected to Z. The output for this condition is Z = AC'. Next consider C = 1 and C' = 0, then we find that TG2 is enabled and B gets selected to the output. The output for this condition is Z = BC. The combined output now becomes Z = AC' + BC. The output expression suggests that the circuit shown in Fig. 3.42 acts as a 2x1 multiplexer. The 2x1 mux using pass transistor logic is shown below.


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