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Sunday, 7 October 2018

Advantages and Disadvantages of ECL Gates

Advantages of ECL Gates 

Since the BJTs of ECL gates operate in the active region, they have the highest speed among all logic families.
ECL gates produce complementary outputs (OR-NOR).
Current switching spikes are not present in power supply leads.
Outputs can be tied together to give the wired-OR function.
Parameters do not vary much with temperature.
The number of functions available from a single chip is high.
Typical supply voltage is –5.2 V.

Disadvantages of ECL Gates

Very low noise-margin (±200 mV).
Highest power dissipation among all logic gates.
Level shifters are required for interfacing with other logic families.
Capacitive loading limits fan out.
ECL gates cost more than that of TTL gates.
VLSI design is difficult as ECL gates require resistors also to be fabricated.

Noise Margin of ECL Gates

The noise margin of ECL gates can be computed as given below:

OFF-state voltage at A, VOFF = 0.3 V

Cut-in voltage, VBEC = 0.5 V   


Noise margin = 0.5 – 0.3 = 0.2 V

This shows that ECL gates have very low noise immunity, i.e., they are easily vulnerable even to very low-level noise voltages.

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