Working Principle of the Two-Input TTL NAND Gate

In TTL circuits also, input transistor T₁ is a multi-emitter transistor driving the phase-splitter transistor T₂. As stated above, this phase-splitter drives the push-pull output transistors T₃ and T₄. The output section, consisting of transistors T₃ and T₄, diode D, and the 100-ohm resistor, is known as a totem-pole configuration, since it looks like a totem-pole with its ups and downs. It may be noted that a totem pole is a stick held by kings, emperors, and holy men in their hands to exhibit their authority. In another type of NAND gate, called the open-collector NAND gate, transistor T₃ and diode D are removed.

Consider the situation when both the inputs A and B are at the logic-0 (0-V input) state, i.e., A = B = 0. In this condition, the base-emitter diodes of the multi-emitter transistor T₁ are forward biased and current flows from +V_CC through the base and emitters of T₁ to ground. This makes the base-collector diode of T₁ reverse biased, and prevents current from flowing into the base of transistor T₂. Since there is no current flow through its base, T₂ remains OFF making its collector current I_C2 = 0, and collector voltage V_C2 = +V_CC (+5 V as standard value for TTL family). We also find that since the collector current of T₂ is zero, its emitter voltage V_Y = 0.

Let us now investigate the states of the totem-pole transistors T₃ and T₄. Since the collector voltage of T₂, V_C2 = V_CC, transistor T₃ turns-on and it acts as a short circuit between V_CC and output point Z.  Also since the emitter voltage of T₂, V_E2 = 0, transistor T₄ remains OFF. Since T₃ is ON and T₄ is OFF, we find that the output Z for the input condition A = B = 0, is +V_CC, or logic 1.

Consider now the situations in which A = 1 and B = 0, or A = 0 and B = 1. In these cases also, one of the diodes is conducting and the input is grounded. So the same arguments given above for the situation A = B = 0 prevails in these cases also.

Now consider the condition A = B = 1. In this case, both the diodes A and B remain reverse biased. So, current flows from +V_CC through the base-collector diode of T₁ into the base of T₂ turning it ON. Collector current of T₂ starts flowing now, developing enough voltage (0.8 V) at its emitter E₂ to turn T₄ ON. Also since T₂ is ON, its collector-emitter voltage drops to the saturation value of V_CES2 = 0.2 V and its collector voltage V_C2 = 0.8 + 0.2 = 1 V.  With diode D present, T₃ remains OFF. However since T₄ is ON, the collector-emitter voltage of T₄, V_CES4 = 0.2 V, and the output Z is at logic 0. Thus for the situation A = B = 1, we have Z = 0. These relations are summed up as shown in Table 3.1. Inspection of the entries in Table 3.1 reveal that the circuit shown in Fig. 3.4 acts as a two-input positive-logic NAND gate.

Truth table of two-input TTL NAND

A	B	Z
0	0	1
0	1	1
1	0	1
1	1	0