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Sunday, 24 November 2019

Semiconductor Memory in Digital Electronics


Numerous developments in semiconductor technology has emerged into large numbers ot LSI and MSI memory devices, called memory chips. Besides being faster and compatible with CPU they are economical also( semiconductor memory is organized as a rectangular array (preferably square array) of storage cells that are integrated on a silicon wafer and are available in DIP packages)tue to this organization any memory cell can be accessed randomly, thus all the semiconductor memories are called Random Access Memory (RAM). The basic meitiory cell may be a flip-flop, or a charge storing element like capacitor that is said to hold logic 1 when charged and logic 0 when discharged. The type of transistors e.g. bipolar, or MOS, or CMOS, used to form a memory cell dictates the storage capacity and speed of a memory chip.

Basic Memory Unit :

A simple block diagram of a memory unit can be drawn as shown in Figure. It contains data bus, address bus and control signals. A bus is a group of parallel conductors whose job is to carry binary information. Each of the conductors carries 1-bit information. The number of bits that a memory data bus carries simultaneously is called memory bus width. Usually, but not necessarily, the memory word length and memory bus widths are same.
Block Diagram of Memory Unit
The m-bit data bus is used to transfer data to and from the memory. The n-bit address bus carries the address of memory locations. An n-bit address bus can access upto 2n storage cells i.e., storage capacity is 2n bits as each cell can store 1-bit. The Read (RD) & Write (WR) signals specify the operation to be performed. As shown the two signals are active low i.e., they are activated when logic '0'. At any time either of the two signals can be activated. In some memory chips read & write controls are available at one signal line. Chip select signal (CS) (sometimes labeled as enable EN also) is used to enable/disable the chip in multiple memory system. It is also a logic low signal. There may be multiple enable signals in a single chip that must be activated simultaneously to enable the chip.

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