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Thursday, 24 October 2019

Pinout of 8086 Microprocessor


Pinout of 8086 Microprocessor is shown in figure below.
8086 can operate in two multimode of operations.

(1) Minimum Mode

8086 Minimum Mode

(2) Maximum Mode
8086 Maximum Mode
At a time, 8086 processor can act as a minimum mode or maximum mode.
MN/MX’ Pin (Pin no: 33) determines the mode of 8086 processor.

When MN/MX’ is in high state, 8086 processor operates at minimum mode.
When MN/MX’ is in low state, 8086 processor operates at maximum mode of operation.

In maximum mode of operation, 8086 processor will act as a Multiprocessor. In uniprocessor system, 8086 processor will do all the operations. In multiprocessor system, more than one processor is connected.

Note: In order to perform the exponential operation, another processor (co processor) is connected in parallel with 8086 (main) processor.

Co Processor of 8086 is 8087: Co Processor is used to perform floating point operation, exponential operations etc.

CLK (Clock):

Clock defines the speed of the processor.
In 8086 Processor, external clock is same as the internal clock.
In 8085 Processor, internal clock is half of the external clock.


NMI and INTL:

8086 processor has two hardware interrupts. In 8086 processor, two pins are provided for interrupts and these are called hardware interrupts. They are NMI and INTR.

INTR – Interrupt Request Signal
NMI – Non Maskable Interrupts

In Non Maskable Interrupts, the programmer cannot change the priority of interrupt. But in maskable interrupts, programmer can change the priority of interrupts.

RD’ is the read signal (Memory read or I/O read).
WR’ is write signal (Memory write or I/O write)

When RD’ is low, that operation is read operation and when WR’ is low, that operation is Write Operation. When M/Io’ is in high state, the operation is I/O operation. When M/Io’ is in high state, the operation is I/O operation. When M/ Io’ is at low state, that operation is memory related.

M/ Io
RD’
WR’
Operation
1
0
1
Memory Read
1
1
0
Memory Write
0
0
1
I/O read
0
1
0
I/O write

HOLD and HLDA:

HOLD is a request signal send by the peripheral devices to the microprocessor to release the control of the system buses.

HLDA is a hold acknowledgement signal; send by the processor to the peripheral devices.

ALE (Address Latch Enable):

ALE is used to demultiplex address/data bus. When ALE is in high state, multiplex bus act as a address bus. When, ALE is in low state, MUX act as a bus.
INTA’ is the interrupt acknowledgement signal.
DT/R’ is the data transmit/receive signal.

DEN’ (Data Enable)

When DEN’ is enabled, that data bus contains a valid data.

RQ’/GT0 and RQ’/ GT1

RQ’/GT0 and RQ’/ GT1 are the bus request/bus grand signal, send by the peripheral devices to the microprocessor.

QS0 and QS1

QS0 and QS1 gives the status of the Q-register.

READY

When READY signal is in low state, the processor will act in the slower state. When READY signal is in high state, the processor can go to the next state.

TEST’

When READY Signal is in low state, TEST’ is in high state.
When TEST’ is in low state, READY is in high state, then only the processor can perform the next state task.

Status Signal during memory segment access

Status Signal
Segment Register
S4
S3
0
0
Extra Segment
0
1
Stack Segment
1
0
Code or No Segment
1
1
Data Segment

Queue Status

Queue Status
Queue Operation
QS1
QS0
0
0
No Operation
0
1
First byte of an opcode from queue
1
0
Empty the Queue
1
1
Subsequent byte from Queue

Status Signal during various machine operation

Status Signal
Machine Cycle
S2
S1
S0
0
0
0
Interrupt acknowledgement
0
0
1
Read I/O Port
0
1
0
Write I/O Port
0
1
1
Halt
1
0
0
Code Access
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
Passive/Inactive

Flags in 8086 Processor:

In 8086, flags are classified into Directional Flag, Conditional Flag and Control Flag.
Flag register keeps the status of Operation.

1. Zero Flag: If the result of an operation is zero, then the zero flag will set and if the result is non zero, then the zero flag will resets.

2. Carry Flag: If the result of an operation contains carry, then the carry flag will set and otherwise it will reset.

3. Overflow Flag: If the result of an operation exceeds the capacity of the memory location, overflow occurs. When overflow occurs, the overflow register will set, otherwise it will resets.

4. Parity Flag: The parity flag will set, if the result is even parity and the parity flag will resets, if the result is odd parity.

5. Sign Flag: If the number is negative, then the sign flag will set  and if the number is positive, sign flag will resets.

6. Auxiliary Carry Flag: If there is carry in the lower byte, the auxiliary flag will set, otherwise it will resets.

7. Directional Flag: When the processor is in auto decrement mode of operation, directional flag will set and when the processor is in auto increment mode, directional flag will reset.

8. Interrupt Flag: At the time of interrupt operation, interrupt flag will set and otherwise it will reset.

9. Single Step Flag: When the processor is in single step operation, single step flag will set, otherwise it will reset.


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