Timing Diagram of MOV Rd Rs Instruction in 8085

Timing diagram for MOV Rd, Rs (or MOV r1, r2) instruction

MOV Rd, Rs instruction moves (copies) the contents of the source register (Rs) into the destination register (Rd). It is a single byte instruction. It has only Opcode Fetch machine cycle. Some examples for MOV Rd, Rs instruction:

1. MOV A, B
2. MOV C, L

The time taken by the processor to execute the Opcode Fetch cycle is 4T (T- states). The first 3 T-states are used for fetching the Opcode from memory and the remaining T-state is used for internal operations by the microprocessor. The timing diagram for MOV Rd, Rs (Opcode Fetch machine cycle) is shown in figure. It has 4 T states.
Timing Diagram of MOV Rd Rs Instruction in 8085 Microprocessor

The steps for machine cycle of MOV Rd, Rs instruction are given in table.

T state
The microprocessor places the higher order 8-bits of the Program Counter on A15 – A8 address bus and the lower order 8-bits of the Program Counter on AD7 – AD0 address / data bus.
The microprocessor makes the ALE signal HIGH and at the middle of T1 state, ALE signal goes LOW.
The status signals are changed as IO/M'= 0, S1 =1 and S0 = 1. These status signals do not change throughout the OF machine cycle.
The microprocessor makes the RD' line LOW to enable memory read (opcode fetch) and increments the Program Counter.
The contents on D7 – D0 (i.e. the Opcode) are placed on the address / data bus.
The microprocessor transfers the Opcode on the address / data bus to Instruction Register (IR).
The microprocessor decodes the instruction.
The data in the register Rs (r2) is moved to the register Rd (r1).

Sreejith Hrishikesan

Sreejith Hrishikesan is a ME post graduate and has been worked as an Assistant Professor in Electronics Department in KMP College of Engineering, Ernakulam. For Assignments and Projects, Whatsapp on 8289838099.

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