In Sections 3.1 to 3.17, we have discussed logic families that belong to the category of *saturating* *logic*. The active devices (BJTs and FETs) used in the logic gates belonging to this category operate in their saturation and cut-off modes. To turn-on and turn-off these devices require more time than devices that operate in their active region of operation. So gates that operate in the saturating mode are relatively slow. This suggests that devices that operate in their active region of operation are much faster than saturating-mode devices. Emitter-coupled logic (ECL) family is a logic family that makes use of differential amplifiers operating in their active mode for the construction of logic gates.

*T*

_{1}and

*T*

_{3 }form the first differential amplifier and

*T*

_{2}and

*T*

_{3 }form the second. These differential amplifiers drive two emitter-follower stages comprising of transistors

*T*

_{4}and

*T*

_{5}to deliver complementary outputs

*Z'*and

*Z*. The load resistance of

*T*

_{3}is 300 ohms. For the ideal OPAMP, the load of

*T*

_{2}must also be of 300 ohms. However, in practice, it will be less than this, as will be shown later.

*collector terminals of its transistors are grounded, and a DC voltage of –5.2 V is applied to the emitters.*This negative supply voltage makes the calculations slightly difficult, since mostly we are familiar with positive supply voltages. However, a systematic approach in this case will give the required results.

^{2}L is also called as

*merged-transistor logic*(MTL).

**Working Principles of the ECL OR-NOR Gate**

*±*200 mV. Also, it dissipates quite a large amount of power as the circuit draws heavy collector current during the entire period of its operation. There is no OFF-state for the ECL gates to reduce power loss.

*fastest logic*circuit prior to the advancement of CMOS chips. Typical speed of ECL gates lie in the range of few GHz. However, currently CMOS chips are available with much higher speed than that of the ECL chips. The very low power and supply-voltage requirements have made CMOS logic more popular now.

Consider Fig. 3.50, which shows the details of the circuit connections and node voltages required for the analysis. Let the input

*A*be at logic-

**0**level. This makes

*T*

_{2}OFF and

*T*

_{3}ON. Let us assume that transistor

*T*

_{3}is operating in its active region. We also assume that its base-emitter voltage

*V*

_{BE3}= 0.7 V. Then from Fig. 3.50, we find that voltage at node

*X*,

*V*

_{X}

*= – V*

_{R}

*– V*

_{BE3}= –1.15 – 0.7= –1.85 volt

*V*

_{1.18 kΩ }

*= –V*

_{X}

*–*(–

*V*

_{EE})

*=*– 1.8 – (–5.2) = 3.35 V

*I*through the 1.18-kΩ resistor is given by

*I*= 3.35 V/1.18 kΩ = 2.84 mA

*flowing through the collector of*

*T*

_{3}will produce a drop of 0.85 V across its 300-ohm collector resistor. Thus, the node

*Y*is at –0.85 V with respect to ground under this condition. Assuming

*T*

_{4}to be ON this time, the voltage output at node

*Z*(emitter of

*T*

_{4}) is:

*V*

_{Z}= –0.85 –0.7 = –1.5 V

**0**level of the ECL gate. Notice that in the logic-

**0**level, all the transistors operate in their

*active region*rather than in cut-off and saturation.

*T*

_{2}(or

*T*

_{1}) is indeed in logic

**0**may now be computed by considering the fact that with

*V*

_{A}, the voltage at point

*A*= −1.5 V and

*V*

_{X}= –1.85 V,

*V*

_{BE1}

*= V*

_{BE2}

*= –1.5 – (1.85) = 0.3 V*

*V*

_{BE1}and

*V*

_{BE2}are the base-emitter voltages of

*T*

_{1}and

*T*

_{2}, respectively. It can be seen that the minimum base-emitter voltage of a transistor to start conducting is 0.4 to 0.5 V and therefore, with

*V*

_{BE}= 0.3 V, both

*T*

_{1}and

*T*

_{2}are indeed in the OFF state.

*A*= 1. This makes

*T*

_{1}ON, and the collector current switches from the 300-ohms resistor to resistor

*R*. With

*T*

_{3}OFF, its collector voltage

*V*

_{Y}is at ground potential, as no current is now flowing through the 300-ohms resistor. Again, with

*T*

_{4}in the active region,

*V*

_{BE4}= 0.7 V. Since

*T*

_{4}is an emitter-follower, the output voltage

*V*

_{Z}=

*V*

_{BE4}= 0.7 V. Thus, the output voltage for logic

**1**at

*A*is given by:

*V*

_{Z}

*= 0.7 V*

**0**level = – 1.5 V

**1**level = – 0.7 V

*V*

_{out-swing}

*=*– 0.7 – (–1.5)

*=*0.85 V

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