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Thursday, 27 September 2018

Voltage Transfer Characteristic of CMOS Inverter

Voltage-Transfer Characteristic of CMOS Inverter

Figure 3.32(a) shows an experimental set-up to plot the input-output voltage-transfer characteristic of a CMOS inverter. For plotting the characteristic, CMOS inverter gates themselves can be used, or CMOS NAND/NOR gates converted into inverters (by short-circuiting their input terminals) can be used. Figure 3.31(a) shows such a connection.




The experiment is conducted by varying the input voltage from 0 to 15 V in steps of, say, 0.1 V each and measuring the corresponding output voltage. The input-output voltage transfer characteristic is then plotted, as shown in Fig. 3.31(b).

In Fig. 3.31 (b), we notice that, when the input voltage Vi VDD/2, the output voltage remains at VDD. This is because, when Vi VDD/2, the NMOS FET will not conduct, but the PMOS FET will conduct and this keeps Vo = +VDD.

When Vi  VDD/2, NMOS starts conducting and PMOS gets turned-off. The input voltage level for transition in CMOS is thus considered to be Vi = VDD/2. This is due to the fact that both the FETs (NMOS and PMOS) are complementary-identical transistors (that is, identical in all respects, except that they are complementary devices). Hence, the turn-on voltage of one device must be equal to the turn-off voltage of the other, which means that this should be half of the voltage swing. As CMOS devices are perfect switches with small ON-resistance, very low drain currents, and fast switching, we find that:

1.      Vo = +VDD, when Vi £ VDD/2 
2.      Vo = 0 V, when Vi ³ VDD/2
3.      Transition from +VDD to 0 volt occurs in zero time, showing a vertical edge in the transfer curve from the OFF-state to the ON-state.

Usually, CMOS gates operate on supply voltages ranging from +5 volts to +15 volts.

Noise Margin of CMOS Gates

Since the logic-1 level and logic-0 level of CMOS gates are +VDD and 0 volt, respectively, and the transition from 0-to-1 or 1-to-0 occurs at VDD/2, we conclude that CMOS gates can tolerate noise level up to VDD/2. Therefore:

                                      Noise margin of CMOS gatesVDD/2


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