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Friday, 14 September 2018

NMOS NOT (Inverter) Gate Circuit


Metal-oxide semiconductor field-effect transistors (MOS FETs) working in their saturation and cut-off modes can be used as logics witches. Both NMOS and PMOS FETs can be used to construct logic gates. One of the major advantages of MOS gates is that all components (such as resistors and capacitors) can be constructed using MOS transistors only. So, we have an all-transistor circuit configuration in NMOS or PMOS gates. This makes it possible to have a very high packing density, easiness in manufacturing, and a lower price.

The NMOS NOT (Inverter) Gate Circuit

Figure 3.20(a) shows an NMOS NOT (inverter) gate using only NMOS transistors. This is a modification of the NOT (inverter) circuit shown in Fig. 3.20(b) constructed using a mechanical switch [(a reproduction of Fig. 2.8(a) for convenience of reference]. In the NMOS inverter, transistor T1 is used to replace mechanical switch A shown in Fig. 3.20(b). Transistor T2, which is of the depletion type, acts as the load resistor of T1, which is of the enhancement type. Note that the gate of T2 is shorted to its source, making VGS = 0. This keeps the transistor in the ohmic region of operation and T2 will act as a load resistance. Note also that this load is located on top of the switching transistor  T1 to produce inversion. The working of the circuit is as follows:

When the input A = 0, T1 is OFF and the output Z = +VDD (logic 1). When A = 1 (+VDD), T1 conducts and Z = 0 volt (logic 0). This means that when the input is A, the output is A' and vice versa. This means that the circuit performs the logic operation of inversion.

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