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Monday, 3 September 2018

The Diode-Transistor Logic Gate

The DL gates have the major defect that they cannot perform inversion (NOT operation). However, we require gates with negation such as NAND and NOR to generate all types of logic functions can be derived using either of these gates alone (see previous blog page). Hence to produce inversion, we connect a transistor in series with the diodes as shown in Fig. 3.2. The DL gate with the addition of one transistor is called as the DTL (diode-transistor logic) gate. As shown in Fig. 3.2, the diodes D1 and D2 perform the AND operation. Transistor T inverts the AND function to produce the NAND function. To ensure proper operation of the circuit a diode D3 is also added, as shown in Fig. 3.2.

The addition of D3 ensures more speedy switching operation. When both D1 and D2 are OFF (i.e., A = B = 1), D3 gets forward biased and turns on transistor T. This makes output Z  = VCES = +0.2 V, where VCES = collector-emitter saturation voltage. We assume that 0.2 V = logic 0. Therefore, when A = 0 and B = 0, A = 0 and B = 1, or B = 0 and A = 1, one or both of the diodes conduct, which make the diode D3 reverse biased. This turns off T making Z = +VCC= logic 1. The operations described here suggest that the circuit shown in Fig. 3.2 performs the basic two-input NAND function. To increase the noise immunity, we may add more diodes in series with D3. Since low voltage levels help to produce voltage swings, this type of logic may be called low-level logic (LLL).

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