Even though CMOS logic gates have very low power dissipation, they have the following limitations:

**1.**They occupy larger area than NMOS gates.

**2.**Due to the larger area, they have larger capacitance.

**3.**Larger capacitance leads to longer delay in switching.

These limitations of the CMOS gates can be reduced by several alternative structures discussed below. These structures resemble the CMOS structure in some way; yet, they are able to reduce the chip area and hence the capacitive delay.

*Pseudo*-NMOS logic,*dynamic*NMOS logic, and*domino*logic are some of these special CMOS structures.###
Pseudo-NMOS (p-NMOS) Logic Gates

Figure 3.32 shows a pseudo-NMOS inverter (p-NMOS NOT) gate, Fig. 3.33 shows a pseudo-NMOS NAND (p-NMOS NAND) gate, and Fig. 3.34 shows a pseudo-NMOS NOR (p-NMOS NOR) gate. As shown in all these figures, there is a block of NMOS FETs, which will contain one or more NMOS transistors, as required by the structure of the gate. However, there will be only one PMOS transistor in any pseudo-NMOS logic, and this will be always grounded.

The p-NMOS circuit is a modification of NMOS circuits with DMOS loads. In p-NMOS circuits, we use a PMOS transistor, instead of the DMOS transistor, as its load. The advantages of using a PMOS load are:

· The circuit retains its basic CMOS structure. Hence, the chip area is minimum compared with the conventional CMOS structure.

· The circuit becomes compatible with CMOS devices.

· The channel resistance of the pseudo-NMOS devices is higher than that of the NMOS devices. Hence, power dissipation is lower for the pseudo devices.

· Pseudo-NMOS circuits are useful in applications where the output remains in logic-

**1**state most of the time.
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