**Noise**

**Margin in Logic Families**

Figure 3.12 shows a TTL NAND gate N

_{1}driving another TTL NAND gate N_{2}. Assume that N_{1}is in the ON-state with*V*_{OLmax}= 0.4 V and N_{2}is in the OFF-state with*V*_{ILmax}= 0.8 V. We find that in between N_{1}and N_{2}, a*maximum noise voltage of +0.4 V**may be**introduced without producing a triggering of N*. This means that the gates working in a noisy atmosphere can tolerate noise voltages of up to + 0.4 V. Similarly, if N_{2}_{1}is OFF with the output voltage*V*_{OH}= 2.4 V, and N_{2}is ON with*V*_{IH }= 2.0 V, the noise margin will be 2.4 − 2.0 = 0.4 V. In this case, the noise voltage*is negative,*as we have to subtract it from the input*.**The margin in the noise voltage levels as explained above is called as the noise margin of the gate.*Typical value of noise margin of TTL gates is 0.4 V. Thus from definition, we find:

+

*V*_{nm}=*V*_{ILmax}–*V*_{OLmax}*‒V*

_{nm}=

*V*

_{OHmax}–

*V*

_{IHmax}

In the case of CMOS, the noise, we find that noise margin is quite high, and hence they highly suitable for working in industrial atmospheres. For CMOS gates,

*V*_{IH}= 7 to 10 volts.*V*_{IL}= 0 to 3 volts,*V*_{OH}=*V*_{DD, }and_{ }*V*_{OL }= 0 to 0.05 volt. Hence,*V*_{nm( CMOS)}*=**V*_{DD}.**Noise Immunity in Logic Families**

*Noise immunity of a TTL gate represents its ability to withstand the interference of noise in its smooth operation.*This is a term derived from the theory of noise voltages. Noise margins of TTL gates were found to be equal to ±0.4 volt. We then say that these gates are immune to noise up to ±0.4 V. Noise immunity of CMOS gates is equal to

*V*

_{DD}.

**Propagation**

**Delay**

*t*

_{P}*Propagation delay is defined as the time taken by a signal to get transmitted through an IC gate.*Typical value of

*t*

_{P}lies in the range of a few nanoseconds.

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