# Integrated Injection Logic Operation

~ on ~ 0 comments**Operating Principles of I**

^{2}L gates
Integrated Injection Logic Operation is explained as follows. To understand the working

**of a typical I**^{2}L gate, consider Fig. 3.46, which consists of five transistors, connected as shown. It can be seen that the base current*I*_{B1}of*T*_{1 }is derived from +*V*_{CC}through the input terminal B. The base-bias current*I*_{B3 }of_{ }transistor*T*_{3}and the collector current*I*_{C1}of*T*_{1}are obtained from the collector current of transistor*T*_{2 }whose injector (emitter) also is connected to +*V*_{CC}.
If

Now, let the input voltage *I*_{B1}is sufficient, the base-to-emitter voltage*V*_{BE1}of*T*_{1}will become the saturation base-emitter voltage*V*_{BES1}(= 0.8 volt), and in this condition, its collector-to-emitter voltage*V*_{CE1}will become saturation base-emitter voltage*V*_{CES1}(= 0.2 volt). So, we find that*T*_{1}is in the ON-state and its output is at logic-**0**level*.*Since*V*_{CES1}= 0.2 volt, the collector current*I*_{C2}of*T*_{2}will flow through the collector of*T*_{1}as*I*_{C1}, and*V*_{BE3}of*T*_{3}= 0.2 V =*V*_{CES1}. This means that at this moment,*T*_{3}is OFF and its collector-emitter voltage*V*_{CE3}= 0.8 volt.*V*

_{i}= 0 V. This makes transistor

*T*

_{1 }to be in OFF-state, and

*I*

_{C2}to flow through the base of

*T*

_{2}. Thus,

*V*

_{BE3}=

*V*

_{BES3 }= 0.8 V. This makes

*V*

_{CE1 }=

*V*

_{BES3 }= logic

**1**, and

*V*

_{CE3 }=

*V*

_{CES3 }= logic

**0**. Thus, the transistors perform inversion operation, with logic

**0**=

*V*

_{CES}= 0.2 V, and logic

**1**=

*V*

_{BES}= 0.8 V. The voltage swing of this gate, therefore, is

*V*

_{s}_{wing}

*=V*

_{BES}

*– V*

_{CES}

*= 0.8 – 0.2 = 0.6 volt*

It can be seen that the logic swing of I

^{2}L gates is very low and this is a major defect of these gates.**I**

^{2}L Gates for Performing Single Function
Figure 3.47 shows a typical I

^{2}L gate which performs the single function of logical inversion (or NOTing). In this case, MOS transistor N_{1}performs the inversion of input*A*to produce the output*A'*. MOS transistor N_{2 }performs inversion of this output and produces*A*again. Thus the circuit shown in Fig. 3.47 performs the operation of double inversion.**I**

^{2}L Gates for Performing Multiple Functions
Figure 3.48 shows a multi-function I

^{2}L gate that can perform the operations of NOT, AND, NAND, and NOR. Notice that only transistors are used. However, an external resistor*R*may be used to derive the currents required for all the PNP transistors from a single +*V*_{CC}supply. Notice that the PNP transistors are not shown in Fig. 3.48.
Transistors

*T*_{1}and*T*_{2}invert inputs*A*and*B*to produce*A'*and*B′*, respectively. One collector of*T*_{1}and one collector of*T*_{2}are now tied together to perform ANDing to produce the NAND output of*A'B′*. Using De Morgan, we find that this operation is also equivalent to the NOR output (*A+B*)*′*.. The other collectors are used to drive*respectively*, transistors*T*_{3}and*T*_{4}, which now invert*A'*and*B′*to give the AND output*AB*.*T*_{5}inverts*AB*to give*(**AB*)*′*. We notice that all logical functions can be obtained from a single*I*^{2}L chip. Since only transistors are used the packing density of*I*^{2}L gate is seen to be comparable to that of the MOS logic; but the voltage swing is only 0.8 − 0.2 = 0.6 volt. Due to this small swing in the output voltage, the I^{2}L technology has not progressed very much, and is not in much use now.**Advantages of**

**I**

^{2}L Gates

· Since I

^{2}L**gates are made up only of****BJTs, they possess high speed of operation.**
· Because only transistors are used for the construction, I

^{2}L**gates have high packing density, and are hence suitable for construction of VLSI circuits.**
· Very low power-supply requirement (1 volt) .

· Low power dissipation.

· Number of processing steps required is small; hence cost per gate is low.

· Several functions are possible on the same chip.

· Using bipolar technology, it is possible to combine I

^{2}L gates with other logic families.**Disadvantages of**

**I**

^{2}L Gates

· Very low voltage swing (≈ 0.6 V); the swing is between

*V*_{BES}(0.8 V) and*V*_{CES }(0.2 V).
· Lower packing density than NMOS.

· Lower noise margin.

· External resistance required for proper functioning.

· I

^{2}L technology, at present, is dormant.
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