Consider the situation when both the
inputs A and B are at the logic0 (0V input) state, i.e., A = B
= 0. In this condition, the baseemitter
diodes of the multiemitter transistor T_{1}
are forward biased and current flows from +V_{CC}
through the base and emitters of T_{1}
to ground. This makes the basecollector diode of T_{1} reverse biased, and prevents current from flowing
into the base of transistor T_{2}.
Since there is no current flow through its base, T_{2} remains OFF making its collector current I_{C2} = 0, and collector
voltage V_{C2} = +V_{CC }(+5 V as standard value
for TTL family). We also find that since the collector current of T_{2} is zero, its emitter
voltage V_{Y} = 0.
Let us now investigate the states of the
totempole transistors T_{3}
and T_{4}. Since the
collector voltage of T_{2}, V_{C2} = V_{CC}, transistor T_{3}
turnson and it acts as a short circuit between V_{CC} and output point
Z. Also since the emitter voltage of
T_{2}, V_{E2 }= 0, transistor T_{4}
remains OFF. Since T_{3} is
ON and T_{4} is OFF, we find
that the output Z for the input
condition A = B = 0, is +V_{CC}, or logic 1.
Consider now the situations in which A = 1
and B = 0, or A = 0 and B = 1. In these cases
also, one of the diodes is conducting and the input is grounded. So the same
arguments given above for the situation A
= B = 0 prevails in these cases also.
Now consider the condition A = B = 1. In this case, both the diodes A and B remain reverse biased. So, current flows from +V_{CC }through the basecollector diode of T_{1} into the base of T_{2} turning it ON. Collector current of T_{2} starts flowing now, developing enough voltage (0.8 V) at its emitter E_{2} to turn T_{4 }ON. Also since T_{2} is ON, its collectoremitter voltage drops to the saturation value of V_{CES2} = 0.2 V and its collector voltage V_{C2} = 0.8 + 0.2 = 1 V. With diode D present, T_{3} remains OFF. However since T_{4} is ON, the collectoremitter voltage of T_{4}, V_{CES4} = 0.2 V, and the output Z is at logic 0. Thus for the situation A = B = 1, we have Z = 0. These relations are summed up as shown in Table 3.1. Inspection of the entries in Table 3.1 reveal that the circuit shown in Fig. 3.4 acts as a twoinput positivelogic NAND gate.
Truth table of twoinput TTL NAND
A

B

Z

0

0

1

0

1

0

1

0

0

1

1

0

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