The Transistor-Transistor Logic Family

The Transistor-Transistor Logic Family

One of the main goals in the design of IC is the reduction in the total area of the chip designed. The components that require larger area in IC technology are resistors and capacitors. So, the major concern in IC design is to reduce the number of resistors and capacitors to as minimum as possible. Also, in IC technology that uses bipolar junction transistors (BJTs) or metal-oxide semiconductor (MOS) transistors, the basic component is the transistor itself. Therefore, if a whole circuit can be constructed using transistors alone, then such a technology can optimize chip-area and reduce the cost of production. However, in transistor-transistor logic (TTL) gates, elimination of resistors has not been made entirely possible. Hence, the density of TTL gates is much less than that of MOS gates. In MOS IC gates, all the components are made up of MOS transistors alone, which make them extremely dense. However, there is a BJT technology useful for manufacturing VLSI gates. This is known as Integrated Injection Logic (I2L), which employs only BJTs. In this section, we shall make a detailed discussion of the TTL family of logic gates.

The Basic Two-Input TTL NAND Gate

Figure 3.3(a) shows the structure of the basic two-input TTL NAND gate. In this basic gate, diodes D1 and D2 of the DTL NAND gate shown in Fig. 3.2, is replaced with a multi-emitter transistor T1. A multi-emitter transistor is a special case of BJT in which there are several individual emitter regions diffused into a single (common) base region. Figure 3.3(b) shows the construction of a two-emitter bipolar junction transistor.

It may be observed that except for the multi-emitter transistor, the rest of the circuit shown in Fig. 3.3(a) resembles that of the two-input DTL gate shown in Fig. 3.2. In the circuit of the basic TTL gate shown in Fig. 3.3(a), we find that the two emitters and the base form diodes D1 and D2, respectively, of the DTL gate shown in Fig. 3.2. Similarly, we notice that the collector-base diode of the multi-emitter transistor T1 forms diode D3 of the new DTL gate.

The working of the circuit shown in Fig. 3.3(a) is similar to that of the DTL gate. When A = B = 0, both the base-emitter diodes of T1 conduct and this reverse biases the base-collector diode of T1. Thus T2 is in the cut-off state and hence its output voltage is +VCC (= 1). The same situation prevails when A = 1 and B = 0, or A = 0 and B = 1. In both these cases, one of the two base-emitter (BE) diodes conducts which reverse biases the collector-base (CB) diode and hence T3 remains in the OFF state producing logic-1 output. However, when A = B = 1, we find both the BE diodes to be reverse biased resulting in the forward biasing of the CB diode, which drives T3 into the ON state. Thus we find that the output Z of T3 is in the logic-0 state.

The discussions given above prove that the basic TTL circuit shown in Fig. 3.3(a) performs the operation of a two-input positive-logic NAND gate.


The Practical Two-Input TTL NAND Gate 

The basic TTL NAND gate shown in Fig. 3.3(a) can not be used to drive loads requiring high current or power. To drive power loads, we usually make use of a push-pull output stage in audio amplifiers. The same concept is incorporated in this case also. Thus to drive power loads, we make use of a power driver circuit, which consists of a phase-splitter circuit driving a push-pull power output stage. The circuit shown in Fig. 3.4 is a modification of the circuit shown Fig. 3.3(a) incorporating these.

The standard (conventional) integrated-circuit (IC) structure of the two-input TTL NAND gate is shown in Fig. 3.4. The first stage consisting of the multi-emitter transistor T1 and the 1.4-kΩ resistor RB1 remains the same as in DL. This stage is used to drive a phase-splitter stage consisting of transistor T3 and resistors RC2 = 1.6 kΩ and RE2 = 1 kΩ, as shown. The phase-splitter in turn drives a class-AB push-pull power output stage consisting of the 100-ohm resistor RC3, transistors T3 and T4, and diode D, as shown in Fig. 3.4. The push-pull output stage is capable of driving ten similar TTL gates connected across its output terminals. Thus the fan-out of TTL gates is 10.

Working Principle of the Two-Input TTL NAND Gate


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