The NMOS NOR Gate Circuit:
Figure 3.24(a) shows a
twoinput NOR gate using NMOS FETs replacing the mechanical switches of the
twoinput NOR gate shown in Fig. 3.24(b).
As in the previous cases, switching transistors T_{1} and T_{2} are of the enhancement type and T_{3}, which acts as the load resistance, is of the depletion type. If A = 0 and B = 0 (i.e., both A and B have 0volt inputs), transistors T_{1 }and T_{2} will remain OFF. Then, the output across the load Z = +V_{DD} (logic 1). However, when A = 0 and B = 1, B = 0 and A = 1, or A = B = 1, either T_{1} or T_{2} or both T_{1} and T_{2} will conduct as the case may be and the output Z = 0 volt (logic 0). These conditions are summarized as given in Table 3.5. The logic relations given in Table 3.5 that the logic gate shown in Fig. 3.24(a) performs the positivelogic NOR operation.
A

B

Z

0
0
1
1

0
1
0
1

1
0
0
0

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