Dynamic NMOS (d-NMOS) Logic Gates:
We know that the number of components required to construct a static circuit can be reduced by converting it into a dynamic circuit. However, to keep the circuit dynamic, we require additional circuitry in the form of memory and clock circuits for which additional expenditure is required. Figure 3.35(a) shows a dynamic NMOS (d-NMOS) NAND gate.
The working of the d-NAND gate can be explained using the equivalent circuits shown in Figs. 3.35(b) and (c), respectively. Let initially the clock C = 0. Then the PMOS transistor Tp gets turned-on (represented by the ON-switch) and the NMOS transistor T3N gets turned-off [represented by an OFF-switch in Fig. 3.35(b)]. In this condition, the NAND operation is disabled. We also notice that in this condition the parasitic load capacitance CL gets charged from +VDD through Tp; this charging operation of CL is known as pre-charging. This is required for speeding up the operation of the gate.
Now, let C = 1. Then Tp gets turned-off and T3N gets turned-on, as shown in Fig. 3.35(c). In this condition, since CL has already been charged, the circuit will not take any additional time to charge it and its speed of operation increases; it also will start to act as a conventional NAND gate.
Advantages of Dynamic Logic Gates:
1. Reduce the static power dissipation of the pseudo-logic gates and other similar gates to zero by allowing the circuit to work only when clock pulses are present.
2. It can be seen that the number of active devices used in a given dynamic logic gate will be less than that of the corresponding CMOS gate. Therefore, the chip area required it for constructing the dynamic logic gate will be less than that of the corresponding CMOS gate.
Disadvantages of Dynamic Logic Gates:
1. More complex circuitry is required for dynamic operation.
2. Clock pulses are required for the operation of the circuit.
3. Due to loading problems, it is difficult to cascade several stages.