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A problem with the dynamic logic is its limitation in cascading several stages. Domino logic, a modification of the dynamic logic, can be used to cascade several stages. The configuration of a dominologic multipleinverter gate is shown in Fig. 3.36. It can be seen from Fig. 3.36 that the circuit is the same as that of the dynamic logic gate with the addition of a CMOS inverter at the output. The addition of the inverter makes the domino logic to produce double inversion (i.e., one by the main transistor block, and the other by the inverter). Hence, only noninverting gates are available in the domino logic system.
Advantages of Domino Logic Gates
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Domino Logic Gates and its Advantages
The working of the circuit shown in Fig. 3.36 can be explained as follows. As in the case of the dynamiclogic NAND gate, here also, when the C = 0, both the NMOS inverter blocks NG_{1} and NG_{2} are in the disabled conditions. At this time, both the PMOS transistors T_{P1} and T_{P2 } are in the ON condition and the outputs Z_{1} and X_{2}, respectively, of NG_{1} and NG_{2} are at +V_{DD }(≡ logic 1). These outputs Y_{1} and Y_{2}, will be inverted by the respective CMOS inverters of I_{1} and I_{2} to give their outputs Z_{1} = Z_{2 }= 0.
Now, when the C = 1, NMOS transistors T_{N2} and T_{N4} get turnedon, and PMOS transistors T_{P1} and T_{P2 }get turnedoff. The outputs Y_{1} and Y_{2} are now dependent on the input A only. If A = 1, then Y_{1} = A' = 0 and Z_{1} = A = 1. But, if A = 0, then the output Y_{1} = 1, and Z_{1} = 0. This produces doubleinversion operation by gate NG_{1}. It may be observed that this operation is repeated by gate NG_{2} to give its output Z_{2} = A. We thus notice that both the gates produce double inversions.
The main aspect in the operation of the domino gate is that, initially as in the case of the dynamic logic, the load capacitor C_{L} is precharged to +V_{DD} through the PMOS transistor. When transition occurs due to the pulse input A, the output Y changes first. The CMOS inverter will then invert this to produce transition in the output Z. The inverter thus ensures that only one transition occurs for singletrigger inputs at A in the case of a singegate system.
Now, suppose we cascade two such dominologic inverter gates, as shown in Fig. 3.36. With a trigger input, Gate NG_{1} produces the required transition, and then after the stipulated propagation delay, Gate NG_{2} produces the final transition.
If several such stages are cascaded in this fashion, the transition takes place one after another, just like thin wooden planks or playing cards fall in a domino. It may be noted that a domino is a special arrangement of several playing cards. In this arrangement, when we give a small push to the first card to the right (or left, depending on the domino arrangement), it falls onto the second card which in turn falls onto the third card and so on in that order. This is called the falling of the domino.
Advantages of Domino Logic Gates
Domino logic has the following advantages:
1. Domino logic structure has much smaller chip area than CMOS structure.
2. Since each gate has an inverter at its output, only one transition will take place for each triggering, as stated before. This avoids glitches (sudden unwanted transitions).
3. Operating speeds are increased due to reduced value of load capacitance.
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Dynamic NMOS (dNMOS) Logic Gates:
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Dynamic NMOS (dNMOS) Logic Gates
We know that the number of components required to construct a static circuit can be reduced by converting it into a dynamic circuit. However, to keep the circuit dynamic, we require additional circuitry in the form of memory and clock circuits for which additional expenditure is required. Figure 3.35(a) shows a dynamic NMOS (dNMOS) NAND gate.
The working of the dNAND gate can be explained using the equivalent circuits shown in Figs. 3.35(b) and (c), respectively. Let initially the clock C = 0. Then the PMOS transistor T_{p} gets turnedon (represented by the ONswitch) and the NMOS transistor T_{3N} gets turnedoff [represented by an OFFswitch in Fig. 3.35(b)]. In this condition, the NAND operation is disabled. We also notice that in this condition the parasitic load capacitance C_{L} gets charged from +V_{DD} through T_{p}; this charging operation of C_{L} is known as precharging. This is required for speeding up the operation of the gate.
Now, let C = 1. Then T_{p} gets turnedoff and T_{3N} gets turnedon, as shown in Fig. 3.35(c). In this condition, since C_{L} has already been charged, the circuit will not take any additional time to charge it and its speed of operation increases; it also will start to act as a conventional NAND gate.
Advantages of Dynamic Logic Gates:
1. Reduce the static power dissipation of the pseudologic gates and other similar gates to zero by allowing the circuit to work only when clock pulses are present.
2. It can be seen that the number of active devices used in a given dynamic logic gate will be less than that of the corresponding CMOS gate. Therefore, the chip area required it for constructing the dynamic logic gate will be less than that of the corresponding CMOS gate.
Disadvantages of Dynamic Logic Gates:
1. More complex circuitry is required for dynamic operation.
2. Clock pulses are required for the operation of the circuit.
3. Due to loading problems, it is difficult to cascade several stages.
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PseudoNMOS (pNMOS) Logic Gates
However, the pseudo circuits have the disadvantage that they possess greater propagation delay than the NMOS devices. Pseudo NMOS Logic Circuit is shown below.
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Pseudo NMOS Logic Circuit
Even though CMOS logic gates have very low power dissipation, they have the following limitations:
1. They occupy larger area than NMOS gates.
2. Due to the larger area, they have larger capacitance.
3. Larger capacitance leads to longer delay in switching.
These limitations of the CMOS gates can be reduced by several alternative structures discussed below. These structures resemble the CMOS structure in some way; yet, they are able to reduce the chip area and hence the capacitive delay. PseudoNMOS logic, dynamic NMOS logic, and domino logic are some of these special CMOS structures.
PseudoNMOS (pNMOS) Logic Gates
Figure 3.32 shows a pseudoNMOS inverter (pNMOS NOT) gate, Fig. 3.33 shows a pseudoNMOS NAND (pNMOS NAND) gate, and Fig. 3.34 shows a pseudoNMOS NOR (pNMOS NOR) gate. As shown in all these figures, there is a block of NMOS FETs, which will contain one or more NMOS transistors, as required by the structure of the gate. However, there will be only one PMOS transistor in any pseudoNMOS logic, and this will be always grounded.
The pNMOS circuit is a modification of NMOS circuits with DMOS loads. In pNMOS circuits, we use a PMOS transistor, instead of the DMOS transistor, as its load. The advantages of using a PMOS load are:
· The circuit retains its basic CMOS structure. Hence, the chip area is minimum compared with the conventional CMOS structure.
· The circuit becomes compatible with CMOS devices.
· The channel resistance of the pseudoNMOS devices is higher than that of the NMOS devices. Hence, power dissipation is lower for the pseudo devices.
· PseudoNMOS circuits are useful in applications where the output remains in logic1 state most of the time.
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Advantages and Disadvantages of CMOS Circuit
The following are the advantages and disadvantages of CMOS circuit are as follows.
Advantages of CMOS Logic Gates
1. Extremely large fanout capability (>50).
2. Lowest power dissipation of all gates (a few nW).
3. Very high noiseimmunity and noisemargin (typically, V_{DD}/2)
4. Lower propagation delay than NMOS.
5. Higher speed than NMOS. Currently, computer chips operating at (or more than) 4 GHz are available in the open market.
6. Large logic swing (=V_{DD}).
7. Only a single power supply (+ V_{DD}) is required.
8. Directly compatible with TTL gates.
9. Temperature stability is excellent.
10. Lowvoltage (1.5 V) chips are now available.
Disadvantages of CMOS Logic Gates
1. Increased cost due to additional processing steps. But, this is being rectified.
2. Packing density less than NMOS. Using PassTransistor logic structure, packing density comparable to or more than that of NMOS gate is possible.
3. MOS chips must be protected from acquiring static charges by keeping the leads shorted. Static charges acquired in leads will destroy the chip. At present this problem has been rectified by using builtin protective devices or circuits.
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VoltageTransfer Characteristic of CMOS Inverter
Noise margin of CMOS gates = V_{DD}/2
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Voltage Transfer Characteristic of CMOS Inverter
Figure 3.32(a) shows an experimental setup to plot the inputoutput voltagetransfer characteristic of a CMOS inverter. For plotting the characteristic, CMOS inverter gates themselves can be used, or CMOS NAND/NOR gates converted into inverters (by shortcircuiting their input terminals) can be used. Figure 3.31(a) shows such a connection.
The experiment is conducted by varying the input voltage from 0 to 15 V in steps of, say, 0.1 V each and measuring the corresponding output voltage. The inputoutput voltage transfer characteristic is then plotted, as shown in Fig. 3.31(b).
In Fig. 3.31 (b), we notice that, when the input voltage V_{i }< V_{DD}/2, the output voltage remains at V_{DD}. This is because, when V_{i }< V_{DD}/2, the NMOS FET will not conduct, but the PMOS FET will conduct and this keeps V_{o} = +V_{DD}.
When V_{i }> V_{DD}/2, NMOS starts conducting and PMOS gets turnedoff. The input voltage level for transition in CMOS is thus considered to be V_{i }= V_{DD}/2. This is due to the fact that both the FETs (NMOS and PMOS) are complementaryidentical transistors (that is, identical in all respects, except that they are complementary devices). Hence, the turnon voltage of one device must be equal to the turnoff voltage of the other, which means that this should be half of the voltage swing. As CMOS devices are perfect switches with small ONresistance, very low drain currents, and fast switching, we find that:
The experiment is conducted by varying the input voltage from 0 to 15 V in steps of, say, 0.1 V each and measuring the corresponding output voltage. The inputoutput voltage transfer characteristic is then plotted, as shown in Fig. 3.31(b).
In Fig. 3.31 (b), we notice that, when the input voltage V_{i }< V_{DD}/2, the output voltage remains at V_{DD}. This is because, when V_{i }< V_{DD}/2, the NMOS FET will not conduct, but the PMOS FET will conduct and this keeps V_{o} = +V_{DD}.
When V_{i }> V_{DD}/2, NMOS starts conducting and PMOS gets turnedoff. The input voltage level for transition in CMOS is thus considered to be V_{i }= V_{DD}/2. This is due to the fact that both the FETs (NMOS and PMOS) are complementaryidentical transistors (that is, identical in all respects, except that they are complementary devices). Hence, the turnon voltage of one device must be equal to the turnoff voltage of the other, which means that this should be half of the voltage swing. As CMOS devices are perfect switches with small ONresistance, very low drain currents, and fast switching, we find that:
1. V_{o} = +V_{DD}, when V_{i} £ V_{DD}/2
2. V_{o} = 0 V, when V_{i} ³ V_{DD}/2
3. Transition from +V_{DD} to 0 volt occurs in zero time, showing a vertical edge in the transfer curve from the OFFstate to the ONstate.
Usually, CMOS gates operate on supply voltages ranging from +5 volts to +15 volts.
Noise Margin of CMOS Gates
Since the logic1 level and logic0 level of CMOS gates are +V_{DD} and 0 volt, respectively, and the transition from 0to1 or 1to0 occurs at V_{DD}/2, we conclude that CMOS gates can tolerate noise level up to V_{DD}/2. Therefore:
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LowPower Dissipation in CMOS Logic Gates
It can be seen from Fig. 3.30(b) that only one of the switches remains closed and the other remains open at any instant under consideration,. This means that, no current will flow through the circuit at any instant of time, and hence no power loss will occur in the circuit. However this is too ambitious a statement to be realized in practice
In actual practice, a very small amount of leakage current will flow through the device, especially when the transistors are turnedon or turnedoff. For example, let initially the PMOS be ON and the NMOS be OFF. We assume that the drain current I_{D} = 0._{ }Now, let a trigger applied to the gate of NMOS turns it ON suddenly. At this time, the PMOS, which was conducting previously, still continues to conduct for a little more time before it turns OFF. So, we find that both the transistors are conducting simultaneously for a very small interval of time. During this period some power will be drained from the battery and dissipated in the transistors. But this is usually negligibly small.
Figure 3.31 shows two situations when both the transistors remain in the ONstate simultaneously; this occurs at transitions points TP_{1} and TP_{2}, as shown. TP_{1} is the instant at which T_{1} jumps up from its ONstate to OFFstate and T_{2} jumps down from its OFFstate to ONstate. Similarly, TP_{2} is the instant at which T_{2} jumps up from its ONstate to OFFstate and T_{1} jumps down from its OFFstate to ONstate.
From data manuals of CMOS gates, it is found that the drain current of CMOS transistors is in the range of nA to pA (10^{−9} to 10^{−12}). Power dissipation of COMOS gates is about a few pW. With the advent of modern technology, packing density of CMOS gates has been found to be extremely high and the speed of operation has reached the GHz range.
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Low Power Dissipation in CMOS Logic Gates
LowPower Dissipation in CMOS Logic Gates
CMOS logic gates are currently the most popular forms of logic gates because of their advantages over other logic families. One of the main features of CMOS gates is its lowpower dissipation capability. This feature is explained below.
CMOS gates are constructed, as explained above, with NMOS upon PMOS or vice versa. For example, consider the CMOS inverter shown in Fig. 3.26. This is redrawn here as shown in Fig. 3.30(a) for illustration. Figure 3.30(b) shows an approximate equivalent inverter network using mechanical switches. In this, we have represented the PMOS transistor using a closed switch and the NMOS transistor using an open switch. We also find that the two switches are ganged together by a push/pull lever, which can be operated to open the PMOS switch and close the NMOS switch or vice versa. Assuming push ≡ logic 0 and pull ≡ logic 1, we find that the circuit shown in Fig. 3.30(b) performs inversion.
It can be seen from Fig. 3.30(b) that only one of the switches remains closed and the other remains open at any instant under consideration,. This means that, no current will flow through the circuit at any instant of time, and hence no power loss will occur in the circuit. However this is too ambitious a statement to be realized in practice
In actual practice, a very small amount of leakage current will flow through the device, especially when the transistors are turnedon or turnedoff. For example, let initially the PMOS be ON and the NMOS be OFF. We assume that the drain current I_{D} = 0._{ }Now, let a trigger applied to the gate of NMOS turns it ON suddenly. At this time, the PMOS, which was conducting previously, still continues to conduct for a little more time before it turns OFF. So, we find that both the transistors are conducting simultaneously for a very small interval of time. During this period some power will be drained from the battery and dissipated in the transistors. But this is usually negligibly small.
Figure 3.31 shows two situations when both the transistors remain in the ONstate simultaneously; this occurs at transitions points TP_{1} and TP_{2}, as shown. TP_{1} is the instant at which T_{1} jumps up from its ONstate to OFFstate and T_{2} jumps down from its OFFstate to ONstate. Similarly, TP_{2} is the instant at which T_{2} jumps up from its ONstate to OFFstate and T_{1} jumps down from its OFFstate to ONstate.
From data manuals of CMOS gates, it is found that the drain current of CMOS transistors is in the range of nA to pA (10^{−9} to 10^{−12}). Power dissipation of COMOS gates is about a few pW. With the advent of modern technology, packing density of CMOS gates has been found to be extremely high and the speed of operation has reached the GHz range.
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Advantages and Disadvantages of NMOS Gates
The following are the advantages and disadvantages of NMOS gates.
Advantages of NMOS gates
1. The number of diffusions steps required is the lowest. Hence, cost per gate is the lowest.
2. Very low power dissipation (on the order of a few nW).
3. Power supply can be varied from 5 V to 15 V possible.
4. Only NMOS transistors are used, no isolationislands are required. Hence, highest packing density of all logic families. Suitable for VSLI, ULSI etc.
5. Large fan out capability (20 gates)
6. Very high noisemargin. Suitable for use in industrial atmosphere.
7. MOS circuits are used as capacitors. They can also be used as resistors.
8. MOS devices are used in chargecoupled devices (CCDs).
Disadvantages of NMOS gates
1. MOS transistors are also capacitors. Hence, speed of operation is lowest due to very high capacitive loading.
2. Large propagation delay per gate.
3. Higher power dissipation than CMOS gates.
4. This technology has not acquired as much popularity as the CMOS technology. CMOS, because of its lower power dissipation and higher speed of operation has replaced NMOS almost completely.
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Advantages of NMOS gates
1. The number of diffusions steps required is the lowest. Hence, cost per gate is the lowest.
2. Very low power dissipation (on the order of a few nW).
3. Power supply can be varied from 5 V to 15 V possible.
4. Only NMOS transistors are used, no isolationislands are required. Hence, highest packing density of all logic families. Suitable for VSLI, ULSI etc.
5. Large fan out capability (20 gates)
6. Very high noisemargin. Suitable for use in industrial atmosphere.
7. MOS circuits are used as capacitors. They can also be used as resistors.
8. MOS devices are used in chargecoupled devices (CCDs).
Disadvantages of NMOS gates
1. MOS transistors are also capacitors. Hence, speed of operation is lowest due to very high capacitive loading.
2. Large propagation delay per gate.
3. Higher power dissipation than CMOS gates.
4. This technology has not acquired as much popularity as the CMOS technology. CMOS, because of its lower power dissipation and higher speed of operation has replaced NMOS almost completely.
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Figure
3.25 shows a multiplelogic NMOS gate, called the ANDORINVERT (AOI) gate.
This is a combination of two NMOS AND gates producing the functions of AB and CD. These two AND gates are connected in parallel so that they
perform an ORing operation. This ANDOR function is then NOTed to produce the
function Z = (AB+CD)′. As shown in Fig.
3.25, transistors T_{1 }and T_{2} form one AND operation and
T_{3} and T_{4} form the other. The
parallel combination of these two pairs will produce the
desired AOI output.
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NMOS ANDORInvert Gate Circuit
NMOS ANDORInvert Gate Circuit
NMOS AOI Gate Circuit 
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As in the previous cases, switching transistors T_{1} and T_{2} are of the enhancement type and T_{3}, which acts as the load resistance, is of the depletion type. If A = 0 and B = 0 (i.e., both A and B have 0volt inputs), transistors T_{1 }and T_{2} will remain OFF. Then, the output across the load Z = +V_{DD} (logic 1). However, when A = 0 and B = 1, B = 0 and A = 1, or A = B = 1, either T_{1} or T_{2} or both T_{1} and T_{2} will conduct as the case may be and the output Z = 0 volt (logic 0). These conditions are summarized as given in Table 3.5. The logic relations given in Table 3.5 that the logic gate shown in Fig. 3.24(a) performs the positivelogic NOR operation.
Table 3.5 NMOS NOR
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NMOS NOR Gate Circuit
The NMOS NOR Gate Circuit:
Figure 3.24(a) shows a
twoinput NOR gate using NMOS FETs replacing the mechanical switches of the
twoinput NOR gate shown in Fig. 3.24(b).
As in the previous cases, switching transistors T_{1} and T_{2} are of the enhancement type and T_{3}, which acts as the load resistance, is of the depletion type. If A = 0 and B = 0 (i.e., both A and B have 0volt inputs), transistors T_{1 }and T_{2} will remain OFF. Then, the output across the load Z = +V_{DD} (logic 1). However, when A = 0 and B = 1, B = 0 and A = 1, or A = B = 1, either T_{1} or T_{2} or both T_{1} and T_{2} will conduct as the case may be and the output Z = 0 volt (logic 0). These conditions are summarized as given in Table 3.5. The logic relations given in Table 3.5 that the logic gate shown in Fig. 3.24(a) performs the positivelogic NOR operation.
A

B

Z

0
0
1
1

0
1
0
1

1
0
0
0

0
NMOS OR Gate Circuit
The NMOS OR Gate Circuit
Figure 3.23(a) shows a twoinput OR gate using NMOS FETs and 3.23(b) shows its equivalent using switches. It may be noticed in this case also that NMOS transistors are used to replace the mechanical switches and the load resistor. We find that, if A = 0 and B = 0 (i.e., A and B have 0volt inputs), transistors T1and T2 will remain OFF. Then, output Z = 0 volt (logic 0). However, when A = 0 and B = 1, or B = 0 and A = 1, or A = B = 1, either one or both of transistors T1 and T2 conduct and develop +VDD, across the load transistor T3. This means that the output Z = logic 1. This may be summarized as given in Table 3.4. The logic relations given in Table 3.4 are seen to be that of the OR operation. So, we conclude that the logic gate shown in Fig. 3.23(a) performs the positivelogic OR function.
Table 3.4 NMOS OR
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Figure 3.23(a) shows a twoinput OR gate using NMOS FETs and 3.23(b) shows its equivalent using switches. It may be noticed in this case also that NMOS transistors are used to replace the mechanical switches and the load resistor. We find that, if A = 0 and B = 0 (i.e., A and B have 0volt inputs), transistors T1and T2 will remain OFF. Then, output Z = 0 volt (logic 0). However, when A = 0 and B = 1, or B = 0 and A = 1, or A = B = 1, either one or both of transistors T1 and T2 conduct and develop +VDD, across the load transistor T3. This means that the output Z = logic 1. This may be summarized as given in Table 3.4. The logic relations given in Table 3.4 are seen to be that of the OR operation. So, we conclude that the logic gate shown in Fig. 3.23(a) performs the positivelogic OR function.
Table 3.4 NMOS OR
A

B

Z

0
0
1
1

0
1
0
1

0
1
1
1

0
NMOS NAND Gate Circuit
The NMOS NAND Gate Circuit
Figure 3.22(a) shows a twoinput NMOS NAND gate circuit. This circuit is a modification of the NAND gate using mechanical switches shown in Fig. 3.22(b). The mechanical switches of Fig. 3.22(b) are replaced with NMOS transistors in Fig. 3.22(a). NMOS transistors T_{2} and T_{3} are of the enhancement type and T_{1}, which acts as the load resistance, is of the depletion type. Note that this load is located on top of the switching transistors T_{2} and T_{3 }to produce inversion. If A = 0 and B = 0 (i.e., A and B have 0volt inputs), transistors T_{2 }and T_{3} will remain OFF. Then, the output Z = +V_{DD} (logic 1). The same situation prevails, when A = 0 and B = 1, or B = 0 and A = 1. Now, if A = B = 1, then both T_{2} and T_{3} will conduct and the output Z = 0. These logic operations are summarized as given in Table 3.3, which suggests that the gate shown in Fig. 3.22(a) is a positivelogic NAND gate. To get a negativelogic NAND gate, we replace the NMOS transistors with PMOS transistors.
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Figure 3.22(a) shows a twoinput NMOS NAND gate circuit. This circuit is a modification of the NAND gate using mechanical switches shown in Fig. 3.22(b). The mechanical switches of Fig. 3.22(b) are replaced with NMOS transistors in Fig. 3.22(a). NMOS transistors T_{2} and T_{3} are of the enhancement type and T_{1}, which acts as the load resistance, is of the depletion type. Note that this load is located on top of the switching transistors T_{2} and T_{3 }to produce inversion. If A = 0 and B = 0 (i.e., A and B have 0volt inputs), transistors T_{2 }and T_{3} will remain OFF. Then, the output Z = +V_{DD} (logic 1). The same situation prevails, when A = 0 and B = 1, or B = 0 and A = 1. Now, if A = B = 1, then both T_{2} and T_{3} will conduct and the output Z = 0. These logic operations are summarized as given in Table 3.3, which suggests that the gate shown in Fig. 3.22(a) is a positivelogic NAND gate. To get a negativelogic NAND gate, we replace the NMOS transistors with PMOS transistors.
Table 3.3 NMOS NAND
A

B

Z

0
0
1
1

0
1
0
1

1
1
1
0

1
The NMOS
AND Gate Circuit
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NMOS AND Gate Circuit
Figure 3.21(a) shows a
twoinput AND gate using NMOS fieldeffect transistors. This diagram is a
modification of the AND gate using switches shown in Fig. 3.21(b). The AND gate
constructed using mechanical switches was discussed in Section 24 using Fig.
2.4. Figure 3.21(b) is a reproduction of Fig. 2.4 for reference. The mechanical
switches of 3.21(b) are replaced with NMOS transistors in Fig. 3.21(a). We find
that in Fig. 3.21(a), if A = 0 and B = 0 (i.e., A and B have 0volt inputs), transistors T_{1 }and T_{2}
will remain in the OFFstate. Then, output Z
= 0 volt (logic 0). The same
situation prevails, when A = 0 and B = 1, or B = 0
and A = 1 (here logic 0 = 0
volt). Now, if A = B = 1,
then both T_{1} and T_{2} conduct and develop +V_{DD}, across the load
transistor T_{3}. This means
that the output Z = logic 1. These may be summarized as given
Table 3.2. The entries given in Table 3.2 are found to be that of the AND
operation. So, we conclude that the logic gate shown in Fig. 3.21(a) performs
the positivelogic AND operation.
Table 3.2 NMOS AND
A

B

Z

0
0
1
1

0
1
0
1

0
0
0
1

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