CMOS NAND Gate Circuit

The CMOS NAND Gate Circuit

As stated earlier, CMOS NAND is a combination of an NMOS NAND gate with a PMOS NOR gate as its load or vice versa. The circuit of the CMOS NAND is shown in Fig. 3.27. As shown in Fig. 3.27, both the input terminals A of transistors T1N and T1P are shorted together to form the single input terminal A. Similarly, both the input terminals B of T2N and T2P are shorted to form the single input B. Let A = 0, B = 0. In this case, both the PMOS transistors conduct and the NMOS transistors remain OFF. So, output Z = +VDD ≡ logic 1. Also, when one of the inputs (A or B) is 0 and the other (B or A) is 1, the same situation prevails. However, if both A = B = 1, then the NMOS FETs conduct and PMOS FETs remain OFF. Then the output falls to logic 0. This is NAND operation.



CMOS Inverter NOT Gate Circuit

THE CMOS TRANSISTOR LOGIC FAMILY

The complementary metal-oxide semiconductor (CMOS) transistor logic gates are manufactured using a combination of  NMOS  and  PMOS  FETs in their complementing modes, For example, a CMOS NAND gate is constructed by connecting an NMOS NAND gate to a PMOS NOR gate in a fashion such that the PNOR becomes the load of the NNAND and vice versa. This means that the load of the NAND gate is the NOR gate and the load of the NOR gate is the NAND gate. It may be noted here that, in the case of the NMOS gates, EMOSFETs were used as the basic gate and a depletion MOSFET was used as the load; a complementary operation of the DMOSFET acting as the basic gate and the EMOSFETS acting as the load is not possible in this case!

It may further be noted here that the NMOS FETs act as positive-logic elements, and the PMOS FETs act as negative-logic elements. For example, in the case of the CMOS NAND structure, the NMOS NAND performs the positive-logic function and the PMOS NOR performs the negative-logic function. Also, from De Morgan’s laws, we know that an NMOS NAND gate is equivalent to a PMOS NOR gate. Then, by combining the complementary structures of the NMOS and PMOS transistors in appropriate fashion, we can construct any desired CMOS logic gate.

CMOS Inverter NOT Gate:

A CMOS inverter can be constructed by connecting a PMOS transistor as the load resistance of an NMOS transistor, as shown in Fig. 3.26. Before starting our discussion on CMOS gates, the following points are to be remembered:

+VDD input at the gate of the NMOS will drive it into saturation, whereas such a voltage at its gate will keep the PMOS OFF.
A 0-V input to the NMOS will turn it OFF, while such a voltage will turn the PMOS ON.

As stated above, when input A = 0 volt (≡ logic 0), the NMOS is OFF, but the PMOS conducts and the output is +VDD (≡ logic 1). When A = +VDD (≡ logic 1), the NMOS conducts but the PMOS  is
OFF. Hence the output Z = 0 volt (≡ logic 0), as it is shorted by T1. Thus we find that the circuit shown in Fig. 3.26 performs the NOT operation.

Advantages and Disadvantages of NMOS Gates

The following are the advantages and disadvantages of NMOS gates.

Advantages of NMOS gates

1. The number of diffusions steps required is the lowest. Hence, cost per gate is the lowest.
2. Very low power dissipation (on the order of a few nW).
3. Power supply can be varied from 5 V to 15 V possible.
4. Only NMOS transistors are used, no isolation-islands are required. Hence, highest  packing density of all logic families. Suitable for VSLI, ULSI etc.
5. Large fan out capability (20 gates)
6. Very high noise-margin. Suitable for use in industrial atmosphere.
7. MOS circuits are used as capacitors. They can also be used as resistors.
8. MOS devices are used in charge-coupled devices (CCDs).

Disadvantages of NMOS gates

1. MOS transistors are also capacitors. Hence, speed of operation is lowest due to very high capacitive loading.
2. Large propagation delay per gate.
3. Higher power dissipation than CMOS gates.
4. This technology has not acquired as much popularity as the CMOS technology. CMOS, because of its lower power dissipation and higher speed of operation has replaced NMOS almost completely.


NMOS AND-OR-Invert Gate Circuit

NMOS AND-OR-Invert Gate Circuit
NMOS AOI Gate Circuit
Figure 3.25 shows a multiple-logic NMOS gate, called the AND-OR-INVERT (AOI) gate. This is a combination of two NMOS AND gates producing the functions of AB and CD. These two AND gates are connected in parallel so that they perform an ORing operation. This AND-OR function is then NOTed to produce the function Z = (AB+CD)′. As shown in Fig. 3.25, transistors T1 and T2 form one AND operation and T3 and T4 form the other. The parallel combination of these two pairs will produce the desired AOI output.


NMOS NOR Gate Circuit

The  NMOS NOR Gate Circuit:

Figure 3.24(a) shows a two-input NOR gate using NMOS FETs replacing the mechanical switches of the two-input NOR gate shown in Fig. 3.24(b).


As in the previous cases, switching transistors T1 and T2 are of the enhancement type and T3, which acts as the load resistance, is of the depletion type. If A = 0 and B = 0 (i.e., both A and B have 0-volt inputs), transistors T1 and T2 will remain OFF. Then, the output across the load Z = +VDD (logic 1). However, when A = 0 and B = 1, B = 0 and A = 1, or A = B = 1, either T1 or T2 or both T1 and T2 will conduct as the case may be and the output Z = 0 volt (logic 0). These conditions are summarized as given in Table 3.5. The logic relations given in Table 3.5 that the logic gate shown in Fig. 3.24(a) performs the positive-logic NOR operation. 

Table 3.5 NMOS NOR

      A
      B
      Z
      0
      0
      1
      1
      0
      1
      0
      1
      1
      0
      0
      0

NMOS OR Gate Circuit

The NMOS OR Gate Circuit 

Figure 3.23(a) shows a two-input OR gate using NMOS FETs and 3.23(b) shows its equivalent using switches. It may be noticed in this case also that NMOS transistors are used to replace the mechanical switches and the load resistor.  We find that, if A = 0 and B = 0 (i.e., A and B have 0-volt inputs), transistors T1and T2 will remain OFF. Then, output Z = 0 volt (logic 0). However, when A = 0 and B = 1, or B = 0 and A = 1, or A = B = 1, either one or both of transistors T1 and T2 conduct and develop +VDD, across the load transistor T3. This means that the output Z = logic 1. This may be summarized as given in Table 3.4. The logic relations given in Table 3.4 are seen to be that of the OR operation. So, we conclude that the logic gate shown in Fig. 3.23(a) performs the positive-logic OR function.
Table 3.4 NMOS OR

      A
      B
      Z
      0
      0
      1
      1
      0
      1
      0
      1
      0
      1
      1
      1

NMOS NAND Gate Circuit

The NMOS NAND Gate Circuit

Figure 3.22(a) shows a two-input NMOS NAND gate circuit. This circuit is a modification of the NAND gate using mechanical switches shown in Fig. 3.22(b). The mechanical switches of Fig. 3.22(b) are replaced with NMOS transistors in Fig. 3.22(a).  NMOS transistors T2 and T3 are of the enhancement type and T1, which acts as the load resistance, is of the depletion type. Note that this load is located on top of the switching transistors T2 and T3 to produce inversion. If A = 0 and B = 0 (i.e., A and B have 0-volt inputs), transistors T2 and T3 will remain OFF. Then, the output Z = +VDD (logic 1). The same situation prevails, when A =  0 and B = 1, or B = 0 and A = 1. Now, if A = B = 1, then both T2 and T3 will conduct and the output Z = 0. These logic operations are summarized as given in Table 3.3, which suggests that the gate shown in Fig. 3.22(a) is a positive-logic NAND gate. To get a negative-logic NAND gate, we replace the NMOS transistors with PMOS transistors.


Table 3.3 NMOS NAND

      A
      B
      Z
      0
      0
      1
      1
      0
      1
      0
      1
      1
      1
      1
      0

NMOS AND Gate Circuit

The NMOS AND Gate Circuit

Figure 3.21(a) shows a two-input AND gate using NMOS field-effect transistors. This diagram is a modification of the AND gate using switches shown in Fig. 3.21(b). The AND gate constructed using mechanical switches was discussed in Section 24 using Fig. 2.4. Figure 3.21(b) is a reproduction of Fig. 2.4 for reference. The mechanical switches of 3.21(b) are replaced with NMOS transistors in Fig. 3.21(a). We find that in Fig. 3.21(a), if A = 0 and B = 0 (i.e., A and B have 0-volt inputs), transistors T1 and T2 will remain in the OFF-state. Then, output Z = 0 volt (logic 0). The same situation prevails, when A = 0 and B = 1, or B = 0 and A = 1 (here logic 0 = 0 volt). Now, if A = B = 1, then both T1 and T2 conduct and develop +VDD, across the load transistor T3. This means that the output Z = logic 1. These may be summarized as given Table 3.2. The entries given in Table 3.2 are found to be that of the AND operation. So, we conclude that the logic gate shown in Fig. 3.21(a)-  performs the positive-logic AND operation.


Table 3.2 NMOS AND

      A
      B
      Z
      0
      0
      1
      1
      0
      1
      0
      1
      0
      0
      0
      1


NMOS NOT (Inverter) Gate Circuit

METAL-OXIDE SEMICONDUCTOR LOGIC GATES

Metal-oxide semiconductor field-effect transistors (MOS FETs) working in their saturation and cut-off modes can be used as logics witches. Both NMOS and PMOS FETs can be used to construct logic gates. One of the major advantages of MOS gates is that all components (such as resistors and capacitors) can be constructed using MOS transistors only. So, we have an all-transistor circuit configuration in NMOS or PMOS gates. This makes it possible to have a very high packing density, easiness in manufacturing, and a lower price.

The NMOS NOT (Inverter) Gate Circuit

Figure 3.20(a) shows an NMOS NOT (inverter) gate using only NMOS transistors. This is a modification of the NOT (inverter) circuit shown in Fig. 3.20(b) constructed using a mechanical switch [(a reproduction of Fig. 2.8(a) for convenience of reference]. In the NMOS inverter, transistor T1 is used to replace mechanical switch A shown in Fig. 3.20(b). Transistor T2, which is of the depletion type, acts as the load resistor of T1, which is of the enhancement type. Note that the gate of T2 is shorted to its source, making VGS = 0. This keeps the transistor in the ohmic region of operation and T2 will act as a load resistance. Note also that this load is located on top of the switching transistor  T1 to produce inversion. The working of the circuit is as follows:

When the input A = 0, T1 is OFF and the output Z = +VDD (logic 1). When A = 1 (+VDD), T1 conducts and Z = 0 volt (logic 0). This means that when the input is A, the output is A' and vice versa. This means that the circuit performs the logic operation of inversion.




Advantages and Disadvantages of TTL Logic Gates

The following are the advantages and disadvantages of TTL logic gates.

Advantages

1.    TTL family is the fastest saturating logic family (working in between the saturation and cut-off modes).  Also, TTL gates are available in a variety of forms, such as high-speed TTL, high-speed Schottky TTL, low-power TTL etc.
2.    Typical supply voltage is only +5 V with a permitted variation of ±0.25 V. At present, TTL gates of 3-volt and even to 1.5-volt supply are possible.
3.    It has good noise immunity. Typical noise-margin is about 0.4 V.
4.    Power dissipation is in the range of several mW only. In the case of low-power Schottky TTL gates, this is less than 2 mW per gate.
5.    TTL gates are compatible with other logic families.
6.    Commercial and military versions of TTL gates are available.
7.    These gates are more freely available in the open market than most other logic families.
8.    Good fan-out; TTL gates can drive up to 10 gates.
9.    TTL gates producing almost all of the logic functions are available in the market.
10.    TTL gates exhibit low output impedance for high/low states.

Disadvantages  

1.      Noise immunity is not very high; so TTL gates cannot be used in applications where large noise voltages exist.
2.      Because of isolation problems, which require more chip space, TTL VLSI circuits are not possible in its conventional form.
3.      Power dissipation of TTL gates is much higher than that of MOS gates.
4.      Cost of TTL gates is higher than that of NMOS/CMOS gates, when MSI and LSI gates are considered.
5.      TTL gates generate transient voltages at switching instants.
6.      Wired-OR capability is not possible for the conventional TTL gates; open-collector gates are required for this application.


High Threshold Logic, HTL Logic Family

High Threshold Logic,  HTL Logic Family

Figure 3.19 shows the circuit configuration of logic gate called high-threshold logic (HTL) gate. The circuit shown in Fig. 3.19 can be employed in environments where noise-interference level is high. This circuit is actually a modified version of the DTL gate with a supply voltage of +15 V, which is very high compared to the TTL supply voltage of +5 V. For the HTL gate, a 6.9-V Zener diode is used as the coupling element between transistors T1 and T2. T1 and T2 perform the NOT operation. Since the coupling Zener diode has a typical breakdown value of 6.9 V, noise of amplitude greater than 7 V alone will be able to produce a switching transition of the gate.  These high-amplitude noise voltages are rare and hence the circuit will safely operate in noise-environments.
At present, HTL logic gates are replaced with NMOS and CMOS gates, which have, higher noise margins and much more packing density than HTL gates. Hence these gates are almost obsolete.


Tri-State Logic Gate and Application of Tri State Buffer

THE TRI-STATE LOGIC GATE

Usually, logic gates have only two states of operation, viz., 0 and 1. In certain applications, we require the use of a third state. This state is known as the high-impedance (high-Z) state. The logic gate with three states of operation is known as a tri-state logic gate. They are used as buffer gates for isolation purposes. Figure 3.17 shows a typical tri-state logic gate, which is a modification of the two-input TTL NAND gate with the addition of diodes D1 and D2 and an inverter gate (in Fig. 3.17, we have not included transistor T1 of the conventional TTL NAND).

Let, initially, the chip-select enable/disable terminal CS = 0. This makes CS′ = 1, which reverse biases the diodes D1 and D2. In this condition, the circuit behaves as a normal NAND gate.

Now, let CS = 1, so that CS′ = 0. Then diodes D1 and D2 become forward biased and we find that the base and collector of T2 are grounded through the ON-diodes. This makes both T3 and T4 to be in the OFF-state and the impedance of the output stage becomes very high. This is the third high-Z state. In such a state, several gates can be ORed together.

Application of Tri State Buffer

Practical application of the tri-state buffer is shown in Fig. 3.18. This is mainly used in bus-line systems of computer chips. In Fig. 3.18, bus lines, represented by thick lines, are used to transfer data from one register to another register. As shown, data from register A can be transferred to any other register connected to the common bus line. From the figure, we find that register B also is connected to the bus line. Register A can be enabled or disabled by using the CS terminal. Those tri-state buffers which we want to operate are enabled and those which we do not want to operate are disabled. Suppose the tri-state gates associated with registers A and B are enabled and some others (not shown in the figure) are disabled. Then data will flow from A to B through the common bus line, but it will not flow into those gates that are disabled.



Open Collector TTL NAND Gate

If transistor T3 is removed from the totem-pole configuration, we get an open-collector TTL gate. Figure 3.15 shows an open-collector TTL NAND gate. This can be converted into a NAND gate by connecting a pull-up resistor across the output terminals P and Q


The Wired-AND (or Wired-OR) Gate


The open collector gate is used for producing the Wired-AND (or Wired-OR) connection. As shown in Fig. 3.16(a), several NAND gates can be ANDed together using an open-collector TTL gate. This results in the Wired-AND (because the ANDing is obtained through the interconnection of the outputs) logic expression:

Z =(AB)¢(CD)¢(EF)¢                                     (3.1)

Figure 3.16(b) shows the shorting of the collector terminals of the output transistors of the three respective NAND gates to form ANDing operation. However, this can also be recognized as a Wired-OR connection because the output Z in Fig. 3.16(b) can be written in the form 

Z = (AB + CD + EF)¢                          (3.2)

Equation (3.2) shows that the circuit shown in Fig. 3.16(a) performs the NORing of several AND gates. Now, applying De-Morgan’s laws on Eq. (3.2), we obtain 

Z =(AB)¢(CD)¢(EF)¢ = (AB + CD + EF)¢                             (3.3)

Inspection of Eq. (3.3) reveals that the output Z shows the ANDing of several NAND gates, which is also equivalent to NORing of several AND gates. The value of the pull-up resistor Rpull-up is determined by the maximum value of the collector current permissible through each of the output transistors

Current Sourcing and Current Sinking in TTL

The difference between current sourcing and current sinking is as follows:

We know that a logic gate will always remain either in the 0 state or in the 1 state. For a TTL gate, when the gate is in the 1 state, its output (transistor T4) is at +VCC. This high output voltage of the gate can drive many other gates connected in parallel to it by supplying the individual currents required to drive them. This operation is called current sourcing, since the output transistor is capable of acting as a current source. Figure 3.13 shows the current-sourcing operation. It is found that in the logic-1 state, a TTL NAND gate can source (deliver) up to 40 mA of current, as shown in the figure.

The sinking operation is illustrated in Fig. 3.14. In the current-sinking process that occurs in the logic-0 state, the output transistor acts as a sink for other gates driven by it. The maximum value of the sinking current of a TTL NAND gate is 16 mA.

Fan-in Capability of IC Gates

Fan-in represents the maximum number of inputs that can be connected to an 1C gate. In effect, it represents the maximum number of input pins in a given logic-gate chip. For example, 7400 IC chip represents a two-input TTL NAND gate. Therefore, we say that the fan-in of 7400 is 2. Similarly, 7430 IC chip has 8 inputs, and hence its fan-in is 8.

Fan-out Capability of IC Gates

Fan-out represents the number of gates that a given IC can drive. To calculate the fan-out capability of a TTL NAND gate, we proceed as follows:
     
It has been computed that the sinking current of a TTL gate is 16 mA. However, the input current required by each driven gate is 1.6 mA in the sinking mode. Thus the 16-mA current of a TTL gate can sink up to a maximum of ten 1.6-mA TTL gates. Therefore:

Fan-out of a typical TTL gate = 16 mA/1.6 mA = 10

In the sourcing mode also, this same value remains applicable because typical sourcing current is 40 mA for the driven gate. Therefore:

Fan-out of a typical TTL gate = 40 mA/4 mA = 10


Noise Margin and Noise Immunity in logic families

Noise Margin in Logic Families

Figure 3.12 shows a TTL NAND gate N1 driving another TTL NAND gate N2. Assume that N1 is in the ON-state with VOLmax = 0.4 V and N2 is in the OFF-state with VILmax = 0.8 V. We find that in between N1 and N2, a maximum noise voltage of +0.4 V may be introduced without producing a triggering of N2. This means that the gates working in a noisy atmosphere can tolerate noise voltages of up to + 0.4 V.  Similarly, if N1 is OFF with the output voltage VOH = 2.4 V, and N2 is ON with VIH = 2.0 V, the noise margin will be 2.4 − 2.0 = 0.4 V. In this case, the noise voltage is negative, as we have to subtract it from the input.
The margin in the noise voltage levels as explained above is called as the noise margin of the gate. Typical value of noise margin of TTL gates is 0.4 V. Thus from definition, we find:

+Vnm  = VILmaxVOLmax
 ‒Vnm  = VOHmaxVIHmax

In the case of CMOS, the noise, we find that noise margin is quite high, and hence they highly suitable for working in industrial atmospheres. For CMOS gates, VIH = 7 to 10 volts. VIL = 0 to 3 volts, VOH = VDD, and VOL = 0 to 0.05 volt. Hence, Vnm( CMOS) = VDD.

Noise Immunity in Logic Families

Noise immunity of a TTL gate represents its ability to withstand the interference of noise in its smooth operation. This is a term derived from the theory of noise voltages. Noise margins of TTL gates were found to be equal to ±0.4 volt. We then say that these gates are immune to noise up to ±0.4 V. Noise immunity of CMOS gates is equal to VDD.

Propagation Delay tP

Propagation delay is defined as the time taken by a signal to get transmitted through an IC gate. Typical value of tP lies in the range of a few nanoseconds.